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preliminary information describes products that are not in full production at the time of printing. specifications are based on design goals and limited characterization. they may change without notice. contact fairchild semiconductor for current information. preliminary information www.fairchildsemi.com features very high performance, low cost adaptive comb-based decoding multiple pin-compatible versions - 3-line, 2-line, and band-split - 8- and 10-bit processing internal digital linestores supports ntsc/pal ?ld and ntsc frame based decoding multiple input formats - ccir-601/624 (d1), d2, cvbs, yc multiple output formats - ccir-601/624 (d1), rgb, yc b c r 10-18 mpps data rate parallel and serial control interface single +5v power supply applications studio television equipment personal computer video input mpeg and jpeg compression inputs description the tmc22x5ya family of digital video decoders offers unprecedented, broadcast-quality video processing perfor- mance in a single chip. it accepts line-locked or subcarrier- locked composite, yc, or d1 digital video and produces dig- ital components in a variety of formats. an internal three-line adaptive comb decoder structure pro- duces optimal picture quality with a wide range of source material. ntsc/pal ?ld and ntsc frame based decoding is supported with external memory. full comb programma- bility allows the user to tailor the decoders response to a particular systems goals. a family of products offers 3-line, 2-line, and simple decod- ers in 8-bit and 10-bit versions?ll in a pin and software- compatible format. serial and parallel control ports are pro- vided. these submicron cmos devices are packaged in a 100-lead metric quad flat pack (mqfp). related products tmc22071 genlocking video digitizer tmc22x9x 8 bit digital video encoders tmc2081 digital video mixer tmc3003 triple 10-bit d/a converter tmc1185 10 bit a/d converter tmc2192 10 bit video encoder tmc2072 enhanced genlocking video digitizer block diagram 65-22x5y-01 input processor output processor adaptive comb filter videoa 9-0 videob 9-0 g/y 9-0 master 1-0 buffer clock hsync vsync ldv dhsync dvsync dref fid 2-0 b/cb 9-0 r/cr 9-0 ser a 1-0 sa 2-0 reset set r/w sda cs scl d 7-0 parallel control serial control global control internal sync pulse generator y/c split0 y/c split1 linestore1 linestore2 y/c split2 chroma demod comb fail burst locked loop tmc22x5ya multistandard digital video decoder three-line adaptive comb decoder family, 8 & 10 bit rev. 0.9.0
tmc22x5ya product specification 2 preliminary information table of contents features ......................................................................1 applications ...............................................................1 description .................................................................1 block diagram ............................................................1 contents .....................................................................2 list of tables and figures ........................................3 general description ...................................................4 input processor...............................................................4 adaptive comb filter.....................................................4 output processor ............................................................5 parallel and serial microprocessor interfaces................5 pin assignments ........................................................5 pin descriptions.........................................................6 control register map.................................................8 control register definitions ...................................11 decoder introduction...............................................40 yc separation ..............................................................40 comb filter architecture for yc separation ...............41 yc line-based comb filters.......................................42 d1 line-based comb filters .......................................42 ntsc frame and field based decoders ...............42 composite frame-based comb filters ........................42 composite field-based comb filters ..........................42 pal field comb decoders ......................................42 composite pal field comb filters.............................42 the tmc22x5ya comb filter architecture ............43 tmc22x5ya functional description.......................44 input processor.............................................................44 bandsplit filter (bsf) ..................................................44 comb filter input.........................................................45 adaptive comb filter...................................................47 comb fails................................................................49 comb fail detection ....................................................49 generation of the comb fail signals .....................50 luma error signals ......................................................50 hue and saturation error signals.................................50 picture correlation .......................................................50 adapting the comb filter ............................................50 xlut ...........................................................................51 digital burst locked loop ..........................................53 color kill counter .......................................................53 pal color frame bit ...................................................55 hue control..................................................................55 system monitoring of the burst loop error ................55 clamp circuit .............................................................. 55 pedestal removal ........................................................ 55 clamp generator ......................................................... 55 luma notch filter ....................................................... 56 matrix .......................................................................... 56 programmable u scalar............................................... 56 programmable v scalar............................................... 56 programmable y scalar............................................... 56 programmable ms scalar............................................ 56 fixed (b-y) and (r-y) scalars ................................... 56 y offset ....................................................................... 57 matrix limiters............................................................ 57 examples of output matrix operation ........................ 57 simple luma color correction ................................... 58 c b c r msb inversion ................................................. 58 output rounding ......................................................... 58 output formats............................................................ 58 decimating c b c r data............................................... 58 multiplexed yc b c r output (trs words inserted)... 58 yc outputs.................................................................. 58 the ldv clock ........................................................... 58 sync pulse generator ............................................. 59 internal field and line numbering scheme ............... 59 timing parameters .................................................. 61 subcarrier programming ............................................. 61 horizontal timing ....................................................... 61 horizontal and vertical timing parameters................ 61 vertical blanking ........................................................ 62 vindo operation ....................................................... 65 video measurement................................................. 65 pixel grab.................................................................... 65 composite line grab .................................................. 67 parallel microprocessor interface ............................... 67 serial control port (r-bus) ......................................... 68 equivalent circuits and threshold levels ............ 71 absolute maximum ratings.................................... 72 operating conditions .............................................. 73 electrical characteristics........................................ 75 switching characteristics ....................................... 76 system performance characteristics .................... 76 programming examples.......................................... 77 programming worksheet ........................................ 81 related products ..................................................... 82 ordering information ............................................... 84
product specification tmc22x5ya 3 preliminary information list of tables and figures table 1. tmc22x5ya decoder family ................. 4 table 2. normalized subcarrier frequency as a function of pixel data rates....... 45 table 3. comb filter architecture ..................... 48 table 4. simple example of an adaptive comb filter architecture ..................... 48 table 5. adaption modes ................................... 51 table 6. xlut input selection ........................... 52 table 7. xlut output function ......................... 52 table 8. xlut special function definitions..... 52 table 9. pal-b,g,h,i bruch blanking sequence .............................. 53 table 10. pal-m bruch blanking sequence ...... 54 table 11. blanking level selection ..................... 55 table 12. adaptive notch threshold control..... 55 table 13. matrix limiters...................................... 57 table 14. output format ...................................... 58 table 15. ntsc field and line numbering ........ 59 table 16. pal b,g,h,i field and line numbering .................................... 59 table 17. pal m field and line numbering ....... 59 table 18. vertical blanking period ...................... 60 table 19. vertical burst blanking period............ 60 table 20. table of line idents, lid[4:0] .............. 60 table 21. timing offsets ...................................... 61 table 22. pal vindo operation .......................... 63 table 23. pixel grab control................................ 66 table 24. parallel port control............................. 67 table 25. serial port addresses .......................... 69 figure 1. logic symbol.......................................... 4 figure 2. pixel data format ................................... 4 figure 3. fundamental decoder block diagram ...................................... 40 figure 4. comparison of the frequency spectrum of ntsc and pal composite video signals .................... 40 figure 5. examples of notch and bandpass filters..................................................... 41 figure 6. ............................................................... 41 figure 7. chrominance vector rotation in pal and ntsc ...................................... 42 figure 8. chrominance vector rotation over 4 fields in ntsc ................................... 42 figure 9. chrominance vector rotation over 4 fields in pal...................................... 42 figure 10. tmc22x5ya line based comb filter architecture ................................ 43 figure 11. input processor .................................... 44 figure 12. complementary bandsplit filter ......... 44 figure 13. bandsplit filter, full frequency response .............................................. 45 figure 14. bandsplit filter, passband response .............................................. 45 figure 15. block diagram of comb filter input ... 46 figure 16. signal flow around the adaptive comb filter ........................................... 47 figure 17. example of a comb fail using a ntsc two line comb filter........................... 49 figure 18. generation of upper and lower comb fail signals ........................................... 50 figure 19. comb filter selection .......................... 51 figure 20. xlut input selection ........................... 52 figure 21. block diagram of digital burst locked loop ......................................... 53 figure 22. gaussian low pass filters.................. 54 figure 23. gaussian lpf passband detail........... 54 figure 24. output processor block diagram....... 55 figure 25. adaptive notch filters ......................... 56 figure 26. luminance notch filter ....................... 56 figure 27. horizontal timing ................................. 61 figure 28. external hsync and vsync timing for field 1(3, 5, or 7) ............................. 62 figure 29. ntsc vertical interval.......................... 62 figure 30. pal-b,g,h,i,n vertical interval............ 62 figure 31. pal-m vertical interval ........................ 63 figure 32. pixel grab locations............................ 64 figure 33. relationship between pixel count and pixel grab value............................ 65 figure 34. microprocessor parallel port ? write timing.......................................... 66 figure 35. microprocessor parallel port read timing.......................................... 68 figure 36. serial port read/write timing............. 69 figure 37. serial interface ? typical byte transfer........................... 70 figure 38. equivalent digital input circuit ........... 71 figure 39. equivalent digital output .................... 71 figure 40. threshold levels for three-state........ 71 figure 41. input timing parameters ..................... 72 figure 42. functional block diagram of the tmc22x5ya g/y, b/u, and r/v output stage...................................................... 73 figure 43. output timing parameters .................. 74
tmc22x5ya product specification 4 preliminary information general description the tmc22x5ya digital decoder can be used as a universal input to digital video processing systems by decoding digital composite video and transcoding digital component inputs into a common data format. the digital comb ?ter decoder implements one of sixteen comb ?ter architectures to produce luminance and color dif- ference component signals which are virtually free of the cross-color and cross-luminance artifacts associated with simple bandsplit ?ter decoders. table 1. tmc22x5ya decoder family because the cost/performance tradeoff varies among applica- tions, the tmc22x5ya decoder has been developed as a family of six parts. they are all assembled in the same package, and ? the same footprint. the register maps are identical. figure 1. logic symbol the devices come in 8- and 10-bit resolution versions (see figure 2 for data alignment between 8- and 10-bit versions). within each resolution version there are three models, offer- ing three-line adaptive comb ?tering, two-line adaptive comb ?tering, and simple decoding. the tmc22153a 10-bit three-line comb ?ter can be programmed to emulate any of the other parts. all prototyping can be performed with this version to evaluate performance tradeoffs, and lower- cost versions are easily substituted in production. input processor the digitized video and clocks provided to the decoder can be either locked to the line frequency or the subcarrier fre- quency of the digitized waveform, providing broadcast qual- ity decoding from the ntsc square pixel rate of 12.27 mhz to the pal four times subcarrier pixel rate of 17.73 mhz. figure 2. pixel data format inputs containing embedded grs (fairchild video input processors), trs words (d1 multiplexed component sig- nals), and trs-id words (deserialized d2 signals) can be used to lock the internal horizontal and vertical state machines to the embedded information. if this information is not provided, external horizontal and vertical syncs are required for all line-locked input formats, and are optional for ntsc inputs locked to four times the subcarrier (4*fsc). a simple sync separator is provided for digitized inputs locked to the subcarrier frequency: the internal sync separa- tor locks to the mid point of syncs during the vertical ?ld group, then ?wheels during the active portion of the ?ld. for this reason, the dhsync and d vsync operations are not guaranteed in subcarrier mode. adaptive comb filter the line based adaptive comb ?ter in the tmc22x5ya adds or subtracts the high frequency data from three adjacent ?ld lines to produce the average of the high frequency luminance by canceling the chrominance signals, which in ?t ?lds of color are 180 degrees apart. unfortunately ?t ?lds of color are rare and, when vertical transitions in the picture occur, the output of the comb ?ter contains a mixture of both high frequency luminance and chrominance, at which time the comb fails. to avoid the comb ?ter artifacts that occur when this happens, three sets of error signals are sent to a user-pro- grammable lookup table, allowing the output of the comb ?- ter to be mixed with the output of an internal bandsplit decoder. to produce these comb fail error signals, the video on each of the inputs to the comb ?ter is passed through a simple bandsplit decoder. the low-frequency portion of the signal is tmc2215ya tmc2205ya function 321321 10-bit data 444 8-bit data 444444 d1 interface 444444 line-locked mode 444444 f sc -locked mode 444444 genlock mode 444444 ntsc frame comb 44 ntsc/pal field comb 44 3-line comb 44 2-line comb 44 44 line grab 44 44 pixel grab 444444 65-22x5ya-02 videoa 9-0 buffer ldv hsync master tmc22x5ya multistandard digital video decoder clock cs vsync r/w d 7-0 a 1-0 videob 9-0 g/y 9-0 b/c b9-0 r/c r9-0 fid 2-0 avout dhsync dvsync ser set reset sa 2-0 sda scl msb lsb va 9 vb 9 g/y 9 b/c b9 r/c r9 va 8 vb 8 g/y 8 b/c b 8 r/c r8 va 2 vb 2 g/y 2 b/c b2 r/c r2 va 1 vb 1 g/y 1 b/c b1 r/c r1 va 0 vb 0 g/y 0 b/c b0 r/c r0 10 bit va 9 vb 9 g/y 9 b/c b9 r/c r9 va 8 vb 8 g/y 8 b/c b 8 r/c r8 va 2 vb 2 g/y 2 b/c b2 r/c r2 n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c 8 bit
product specification tmc22x5ya 5 preliminary information assumed to be luminance and the high frequency portion is processed as chrominance to ?d the magnitude and phase of the chrominance vector. these three components are then compared across the (0h & 1h) and (1h & 2h) taps of the comb ?ter to produce the difference in luminance, chromi- nance magnitude, and chrominance phase. these differences are then translated in the user-programmable lookup table to produce the ??signal which controls the complementary mix between the output of the comb ?ter and the simple bandsplit decoder. that is, the ??signals controls how much of the combed high frequency luminance signal is sub- tracted from the simple bandsplit chrominance for chroma combs, or added to the low frequency output of the bandsplit for luma comb ?ters. output processor the demodulated chrominance signal and the luminance signal are passed through a programmable output matrix, producing rgb, yuv, or yc b c r . when the clock is at 27mhz, a d1 signal can be produced on the r/v output with the embedded trs words ?ed to the external hsync and vsync timing. parallel and serial microprocessor interfaces the parallel microprocessor interface employs 12 pins, the serial port uses 5. a single pin, ser , selects between the two interface modes. in parallel interface mode, one address line is decoded for access to the internal control register and its pointer. controls are reached by loading a desired address through the 8-bit d 7-0 port, followed by the desired data (read or write) for that address. the control register address pointer auto-increments to address 3fh and then remains there. a 2-line serial interface may also be used for initialization and control. the same set of registers accessed by the paral- lel port is available to the serial port. the device address in the serial interface is selected via pins sa 2-0 . the reset pin sets all internal state machines to their ini- tialized conditions and places the decoder in a power-down mode. all register data are maintained while in power-down mode. pin assignments g/y 1 g/y 0 ldv gnd v dd b/cb 9 b/cb 8 b/cb 7 b/cb 6 b/cb 5 b/cb 4 b/cb 3 b/cb 2 b/cb 1 b/cb 0 gnd v dd r/cr 9 r/cr 8 r/cr 7 r/cr 6 r/cr 5 r/cr 4 r/cr 3 r/cr 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 r/cr 1 r/cr 0 gnd v dd dref fid 0 fid 1 fid 2 dhsync dvsync d 0 d 1 d 2 gnd v dd d 3 d 4 d 5 d 6 d 7 gnd v dd hsync vsync buffer 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pin name pin name reset set ser sa 0 sa 1 sa 2 gnd sda scl cs r/w a 0 a 1 gnd v dd videob 0 videob 1 videob 2 videob 3 videob 4 videob 5 videob 6 videob 7 videob 8 videob 9 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 gnd videoa 0 videoa 1 videoa 2 videoa 3 videoa 4 videoa 5 videoa 6 videoa 7 videoa 8 videoa 9 master 0 master 1 clock gnd v dd gnd g/y 9 g/y 8 g/y 7 g/y 6 g/y 5 g/y 4 g/y 3 g/y 2 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pin name pin name 1 30 65-22x5y-03 31 50 51 80 81 100
tmc22x5ya product specification 6 preliminary information pin descriptions pin name pin number value pin function description inputs videoa 9-0 86, 85, 84, 83, 82, 81, 80, 79, 78, 77 ttl video input a. an 8 or 10 bit data input to the input multiplexer. for 8-bit versions (tmc2205ya) the data are left-justified (videoa 9-2 ). videob 9-0 75, 74, 73, 72, 71, 70, 69, 68, 67, 66 ttl video input b. an 8 or 10 bit data input to the input multiplexer. for 8-bit versions (tmc2205ya) the data are left-justified (videob 9-2 ). vsync 49 ttl vertical sync input. a vertical sync signal (active low) occurring at the start of the first vertical sync pulse in a vertical field group. a falling edge of vsync which is coincident with a falling edge of hsync indicates field 1. this signal is active only when spgip 1-0 = 00. hsync 48 ttl horizontal sync input. a horizontal sync signal (active low) occurring at the falling edge of the video sync. this signal is active only when spgip 1-0 = 00. master 1-0 88, 87 ttl master decoder control. 00 adaptive comb decoder 01 simple bandsplit decoder 10 reserved 11 flat notched luma and simple bandsplit chroma buffer 50 ttl control register select. this signal switches between two sets of registers which control the gain or hue values in the output matrix. when buffer = 0, registers 17-1f are active. when buffer = 1, registers 27-2f take control. clock 89 ttl master processing clock. the clock signal can either be at twice the pixel data rate in the line locked modes, or at four times the subcarrier frequency in the subcarrier mode. the interpretation of the clock signal is set by the cksel register bit. set 52 ttl programmable function pin. the function specified by the set register is active when set is low. the decoder returns to its previous operation when set goes high. outputs g/y 9-0 93, 94, 95, 96, 97, 98, 99, 100, 1, 2 ttl green or luminance digital output. for 8-bit versions (tmc2205ya) the data are left-justified (g/y 9-2 ). b/c b9-0 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 ttl blue or c b digital output. for 8-bit versions (tmc2205y) the data are left-justified (b/c b 9-2 ). r/c r9-0 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 ttl red or c r digital output. for 8-bit versions (tmc2205ya) the data are left-justified (r/c r 9-2 ). dvsync 35 ttl vertical sync output. the dvsync signal occurs once per field and lasts for 1 video line. dhsync 34 ttl horizontal sync output. the dhsync signal occurs once per line and lasts for 64 clock periods. ldv 3 ttl data synchronization output. ldv can be an internally or externally generated clock signal. the internal ldv signal is produced when the clock input is at twice the pixel data rate (pxck); and is a pixel data rate clock phase locked to the falling edge of the hsync. the external ldv can be selected under software control, and must be at the clock, or a sub multiple of the clock, frequency.
product specification tmc22x5ya 7 preliminary information dref 30 ttl decoder reference signal. this is a dual function pin, controlled by register 24, that can function as an active video output indicator or output as a clamp pulse. when set to the active video output function, the dref pin is high during the video portion of each line and low during the horizontal and vertical blanking levels. when set to output a clamp pulse, the clamp pulse is controlled by register 24 and 25 allowing a user to program when a 0.5 m sec pulse is output relative to hsync. fid 2-0 33, 32, 31 ttl field identification output. a 3 bit field ident from the drs signal. m p interface d 7-0 45, 44, 43, 42, 41, 38, 37, 36 ttl parallel control port data i/o. all control parameters are loaded into and read back over this 8 bit data port. a 1-0 63, 62 ttl parallel control port address inputs. these pins govern whether the microprocessor interface selects a table/register address or reads/ writes table/register contents. cs 60 ttl parallel control port chip select. when cs is high the microprocessor interface port, d 7-0 , is set to high impedance and ignored. when cs is low, the microprocessor can read or write parameters over d 7-0 . r/w 61 ttl parallel control port read/write control. when r/w and cs are low, the microprocessor can write to the control registers or xlut over d 7-0 . when r/w is high and cs is low, it can read the contents of any selected xlut address or control register over d 7-0 . reset 51 ttl chip master reset. bringing reset low sets the software reset control bit, sreset , low and disables the digital outputs. if hreset is low the decoder outputs remain disabled after reset goes high until the sreset bit is set high by the host. if hreset is high when reset goes high the decoder the internal state machines are enabled. ser 53 ttl serial/parallel interface select. this pin will select between a parallel (high) or serial (low) interface port. sda 58 r-bus serial data interface. bi-directional serial interface to the control port. scl 59 r-bus serial interface clock. sa 2-0 56, 55, 54 ttl serial address. three bits providing the lsbs of the serial chip id used to identify the decoder. power supply v dd 5, 17, 29, 40, 47, 65, 91 +5 v power supply. positive power supply for digital circuits, +5v. gnd 4, 16, 28, 39, 46, 57, 64, 76, 90, 92 0.0 v ground. ground for digital circuits, 0v. pin descriptions (cont.) pin name pin number value pin function description
tmc22x5ya product specification 8 preliminary information control register map the tmc22x5ya is initialized and controlled by a set of registers which determine the operating modes. an external controller is employed to write and read the control registers through either the 8-bit parallel or 2-line serial interface port. the parallel port, d 7-0 , is governed by pins cs , r/w , and a 1-0 . the serial port is controlled by sda and scl. reg bit name function global control 00 7 srst software reset 00 6 hrst hardware reset 00 5-3 set set pin function 00 2 dhven output h&v sync enable 00 1-0 std selects video standard input processor control 01 7 reserved, set to zero 01 6 ipmux input mux control 01 5 ip8b 8 bit input format 01 4 tden trs detect enable 01 3 tblk trs blank enable 01 2 ipcmsb chroma input msb invert 01 1 abmux ab mux control 01 0 cksel input clock rate select burst loop control 02 7 bllrst bll auto. reset enable 02 6 vipen video input processor enable 02 5-4 lock global lock mode 02 3 blm bll lock mode 02 2 kild color kill disable 02 1 dmodby demod bypass 02 0 cint c b c r interpolation enable chroma processor control 03 7-5 blfs burst loop filter select 03 4 ccen chroma coring enable 03 3-2 ccor chroma coring threshold 03 1 gauby gaussian filter bypass 03 0 gausel gaussian filter select burst threshold 04 7-0 bth burst threshold pedestal 05 7-0 ped pedestal level luma processor control 06 7-6 reserved, set to zero 06 5 anen adaptive notch enable 06 4 anr adaptive notch rounding 06 3-2 ant adaptive notch threshold 06 1 ansel adaptive notch select 06 0 notch notch enable comb processor control 07 7 ls1by line store 1 bypass 07 6 ls1in line store 1 input 07 5 ls2dly line store 2 delay 07 4 split line store 2 data width 07 3 bsfby bandsplit filter bypass 07 2 bsfsel bandsplit filter select 07 1 bsfmsb inverts msb of bandsplit filter 07 0 grsdly delays input to grs decode by 1h mid-sync level 08 7-0 mids mid-sync level extended drs 09 7-4 pckf clock rate 09 3-0 vstd video standard output control 0a 7 op8b output rounded to 8 bits 0a 6-5 oplmt output limit select 0a 4-3 msen mixed sync enable 0a 2 opcmsb chroma output msb invert 0a 1 ybal luma color correction 0a 0 buren output burst enable 0b 7 fmt422 enables c b c r output mux 0b 6 cdec c b c r decimation enable 0b 5 yuvt enables d1 output 0b 4-2 reserved, set to zero 0b 1 drsen drs output enable 0b 0 drsck drs data rate comb filter control 0c 7-6 adapt adaption mode 0c 5 yces yc input error signal control 0c 4 ycsel luma/chroma comb filter select 0c 3-0 comb comb filter architecture reg bit name function
product specification tmc22x5ya 9 preliminary information 0d 7-6 cest chroma error signal transform 0d 5 cesg chroma error signal gain 0d 4 yesg luma error signal gain 0d 3 cestby chroma error signal bypass 0d 2 xfen xlut filter enable 0d 1 fast adaption speed select 0d 0 ywby luma weighting bypass 0e 7-6 xip xlut input select 0e 5-4 xsf xlut special function 0e 3-2 ymux y output select 0e 1-0 cmux c output select 0f 7 reserved, set to zero 0f 6-5 cat adaption threshold 0f 4 dces d1 c b c r error signal 0f 3-2 ipcf comb filter input select 0f 1 yccomp yc or composite input select 0f 0 sync sync processor select sync pulse generator 10 7-0 sts 7-0 sync to sync 8 lsbs 11 7-0 stb sync to burst 12 7-0 btv burst to video 13 7-0 av 7-0 active video line 8 lsbs 14 7-6 reserved, set to zero 14 5-4 av 9-8 active video line 2 msbs 14 3 reserved, set to zero 14 2-0 sts 10-8 sync to sync 3 msbs 15 7 reserved, set to zero 15 6-2 vindo number of lines in vertical window 15 1 vdiv action inside vindo 15 0 vdov action outside vindo 16 7-6 reserved, set to zero 16 5-4 nfdly new field detect delay 16 3-2 spgip spg input select 16 1-0 msip mixed sync separator input select buffered register set 0 active when buffer pin set low 17 7-0 sg0 7-0 msync gain, 8 lsbs 18 7-0 yg0 7-0 y gain, 8 lsbs 19 7-0 ug0 7-0 u gain, 8 lsbs reg bit name function 1a 7-0 vg0 7-0 v gain, 8 lsbs 1b 7-6 yg0 9-8 y gain, 2 msbs 1b 5-3 ug0 10-8 u gain, 3 msbs 1b 2 reserved, set to zero 1b 1-0 vg0 9-8 v gain, 2 msbs 1c 7-0 yoff0 7-0 y offset, 8 lsbs 1d 7-3 reserved, set to zero 1d 2 yoff0 8 y offset, msb 1d 1-0 sg0 7-0 msync gain, 2 msbs 1e 7-1 sysph0 6-0 7 lsbs of phase 1e 0 vaxiso v axis flip 1f 7-0 sysph0 14-7 8 msbs of phase normalized subcarrier frequency 20 7-4 fsc 3-0 bottom 4 bits of f sc 20 3-0 reserved, set to zero 21 7-0 fsc 11-4 lower 8 bits of f sc 22 7-0 fsc 19-12 middle 8 bits of f sc 23 7-0 fsc 27-20 top 8 bits of f sc clamp control 24 7 drfsel clamp pulse enable 24 6 pfltby phase filter enable 24 5-4 clpsel 1-0 int. clamp selection 24 3 vclpen clamp bypass 24 2-0 band 2-0 clamp offset 25 7-0 cpdly 7-0 clamp pulse delay output format control 26 7-6 reserved, set to zero 26 5 ldvio ldv clock select 26 4 opcks output clock select 26 3 dpcen dpc enable 26 2-0 dpc decoder product code buffered register set 1 active when buffer pin set high 27 7-0 sg1 7-0 msync gain, 8 lsbs 28 7-0 yg1 7-0 y gain, 8 lsbs 29 7-0 ug1 7-0 u gain, 8 lsbs 2a 7-0 vg1 7-0 v gain, 8 lsbs 2b 7-6 yg1 9-8 y gain, 2 msbs 2b 5-3 ug1 10-8 u gain, 3 msbs 2b 2 reserved, set to zero 2b 1-0 vg1 9-8 v gain, 2 msbs 2c 7-0 yoff1 7-0 y offset, 8 lsbs 2d 7-3 reserved, set to zero reg bit name function
tmc22x5ya product specification 10 preliminary information 2d 2 yoff1 8 y offset, msb 2d 1-0 sg1 7-0 msync gain, 2 msbs 2e 7-1 sysph1 6-0 7 lsbs of phase 2e 0 vaxis1 v axis flip 2f 7-0 sysph1 14-7 8 msbs of phase video measurement 30 7 set to zero 30 6 lgf line grab flag 30 5 lgen line grab enable 30 4 lgext ext line grab enable 30 3 reserved, set to zero 30 2 pgg pixel grab gate 30 1 pgen pixel grab enable 30 0 pgext ext pixel grab enable 31 7-0 pg 7-0 pixel grab, 8 lsbs 32 7-0 lg 7-0 line grab, 8 lsbs 33 7 reserved, set to zero 33 6-4 fg field grab number 33 3 lg 8 msb of line grab 33 2-0 pg 10-8 pixel grab, 3 msbs 34 7-0 gy 9-2 g/y grab, 8 msbs 35 7-0 bu 9-2 b/u grab, 8 msbs 36 7-0 rv 9-2 r/v grab, 8 msbs 37 7-6 reserved 37 5-4 gy 1-0 g/y grab, 2 lsbs 37 3-2 bu 1-0 b/u grab, 2 lsbs 37 1-0 rv 1-0 r/v grab, 2 lsbs 38 7-0 y 9-2 luma grab, 8 msbs 39 7-0 m 9-2 msync grab, 8 msbs 3a 7-0 u 9-2 u grab, 8 msbs 3b 7-0 v 9-2 v grab, 8 msbs 3c 7-6 y 1-0 luma grab, 2 lsbs 3c 5-4 m 1-0 msync grab, 2 lsbs 3c 3-2 u 1-0 u grab, 2 lsbs 3c 1-0 v 1-0 v grab, 2 lsbs test control 3d 7-0 test must be set to zero 3e 7-0 test must be set to zero vertical blanking control 3f 7 vbit20 v bit control 3f 6 peddis pedestal control 3f 5-0 ccden 5-0 closed caption control auto-increment stops at 3f reg bit name function notes: 1. functions are listed in the order of reading and writing. 2. for each register listed above up to register 3f, all bits not specified are reserved and must be set to zero to ensure proper operation. status - read only 40 7-0 ddsph dds phase, 8 msbs 41 7 linest pixel count reset 41 6 bgst start of burst gate 41 5 vact2 half line flag 41 4 palodd pal ident 41 3 vfly vertical count reset 41 2 fgrab field grab 41 1 lgrab line grab 41 0 pgrab pixel grab 42 7 fld field flag (f in d1 output) 42 6 vblk vertical blanking (v in d1 output) 42 5 hblk horizontal blanking (h in d1 output) 42 4-0 lid line identification 43 7 ygo y/g overflow 43 6 ygu y/g underflow 43 5 ubo c b /b overflow 43 4 ubu c b /b underflow 43 3 vro c r /r overflow 43 2 vru c r /r underflow 43 1-0 reserved 44 7 mono color kill active 44 6-0 fperr frequency/phase error 45 7-0 drs drs signal 46 7-0 partid reads back xx h 47 7-0 revid revision number 48- 4a 7-0 reserved 4b 7 pkill phase kill from comb fail 4b 6-5 cfstat comb filter status 4b 4-0 xop xlut output 4c- ff 7-0 reserved reg bit name function
product specification tmc22x5ya 11 preliminary information control register de?itions global control register (00) 76543210 srst hrst set dhven std reg bit name description 00 7 srst software reset. when low, resets and holds internal state machines and disables outputs. when high (normal), starts and runs state machines and enables outputs. this bit is ignored while hrst is high. 00 6 hrst hardware reset. when hrst is high, srst is forced low when reset pin is taken low. state machines are reset and held. when hrst is low the reset pin can be taken high at any time. the state machines remain disabled until srst is programmed high. when hrst is high the state machines are enabled as soon as the reset pin goes high. 00 5-3 set set pin function. these bits control the set function when the set pin goes low. a = all outputs high-impedance b = internal state machines c = burst locked loop the first set pulse after a software or hardware reset, with set = 111, causes a toggle to set = 010. 00 2 dhven output h&v sync enable. disables dhsync and dvsync signals when high. 00 1-0 std selects video standard. selects video standard. set function 000 reset and hold a, b, & c. 001 set output to blue and flywheel b & c. (rgb outputs) set output to "color" and flywheel b & c (yc b c r outputs) 010 hold a, lock b & c to external input 011 reset c only 100 reset b & c 101 set output to blue and lock b & c to input video (rgb output) 110 line and pixel grab depending on vmcr 6-0 (reg 30) 111 toggle reset function of set = 010. for each set = 0 pulse the chip operation will change from normal to that of set = 010 or visa versa. set function 00 ntsc 01 reserved 10 pal/m 11 all pal standards except pal/m
tmc22x5ya product specification 12 preliminary information control register de?itions (continued) input processor control (01) 76543210 reserved ipmux ip8b tden tblk ipcmsb abmux cksel reg bit name description 01 7 reserved reserved, set to zero. 01 6 ipmux input mux control. used to select the video input processor, d1, or d2 data as the va input to the input processor. videoa is selected for va and videob is selected for vb when ipmux is set low. videob is selected for va and videoa for vb when ipmux is set high. for yc inputs, the luma data must be passed through the va input and chroma through the vb input. ipmux should be set low for line locked composite inputs. 01 5 ip8b 8 bit input format. bottom two bits of inputs videoa 9-0 and videob 9-0 are set to zero when high. 01 4 tden trs detect enable. when high, the trs words embedded in incoming video are used to reset the horizontal and vertical state machines. when low the externally provided or internally generated hsync and vsync are used to reset the horizontal and vertical state machines. 01 3 tblk trs blank enable. blanks the trs and aux data words when high. for line locked and d1 data, the trs and aux data words are set to the luma and chroma blanking levels as appropriate. for d2 (4*f sc ) data, the trs and aux data words are set to the sync tip level. 01 2 ipcmsb chroma input msb invert. the msb of the chroma or c b c r data are inverted when high. 01 1 abmux ab mux control. selects the primary and secondary inputs to the decoder from the da and db outputs of the input processor. when abmux is low, da is selected as the primary and db as the secondary decoder input. 01 0 cksel input clock rate select. set high for line locked clocks and low for subcarrier locked clocks. line locked clocks should be at twice the pixel data rate, and the subcarrier clock should be at four times the subcarrier frequency.
product specification tmc22x5ya 13 preliminary information control register de?itions ( continued) burst loop control (02) 76543210 bllrst vipen lock blm kild dmodby cint reg bit name description 02 7 bllrst bll reset enable. when low, the automatic bll reset is disabled. when high, the bll will be reset if the bll loses lock and fails to reacquire lock within 8 fields. 02 6 vipen video input processor enable. selects interface protocol for fairchild video input devices. active only when lock 1-0 = 10. 02 5-4 lock global lock mode. sets the decoder locking mode. 02 3 blm bll lock mode. sets the decoder burst locking mode. 02 2 kild color kill disable. color killer is disabled when high. 02 1 dmodby demod bypass. chroma data bypasses the demodulator when high. 02 0 cint c b c r interpolation enable. interpolation of c b c r input data from 0:2:2 to 0:4:4 is enabled when high. vipen function 0 video input processor interface 1 tmc22071 interface lock function 00 line locked mode 01 subcarrier locked mode 10 video input processor mode 11 d1 mode blm function 0 frequency lock 1 phase lock
tmc22x5ya product specification 14 preliminary information control register de?itions (continued) chroma processor control (03) 76543210 blfs ccen ccor gauby gausel reg bit name description 03 7-5 blfs burst loop filter select. 03 4 ccen chroma coring enable. enables chroma coring when high. 03 3-2 ccor chroma coring threshold. sets the chroma coring threshold. 03 1 gauby gaussian filter bypass. the chroma data bypasses the gaussian lpf when high. 03 0 gausel gaussian lpf select. selects the gaussian filter response to be used on the demodulated chrominance. see figure 22 for filter responses. blfs f s (mpps) recommended criteria 000 13.5 pal, line-locked yc 000 15 pal, line-locked yc 001 12.27 ntsc, line-locked yc 001 13.5 pal, line-locked composite 010 13.5 ntsc, line-locked yc 010 15 pal, line-locked composite 011 14.32 ntsc, subcarrier-locked yc 011 17.73 pal, subcarrier-locked composite 100 17.73 pal, subcarrier-locked yc 101 13.5 ntsc, line-locked composite 110 12.27 ntsc, line-locked composite 111 14.32 ntsc, subcarrier-locked composite ccor function 00 1 lsb 01 2 lsb 10 3 lsb 11 4 lsb gausel function 0 select gaussian lpf resp. 2 1 select gaussian lpf resp. 1
product specification tmc22x5ya 15 preliminary information control register de?itions (continued) burst threshold (04) 76543210 bth reg bit name description 04 7-0 bth burst threshold. the 8 bit value to be compared against the demodulated u and v component data. if over 127 lines occur in a field in which the burst is below this threshold, then the color is set to chroma black for the next field. pedestal (05) 76543210 ped reg bit name description 05 7-0 ped pedestal level. an 8 bit magnitude subtracted from the luma data to remove the setup before processing by the output matrix. luma processor control (06) 76543210 reserved anen anr ant ysel notch reg bit name description 06 7-6 reserved reserved, set to zero. 06 5 anen adaptive notch enable. enables adaptive notch when high. 06 4 anr adaptive notch rounding. sets adaptive notch rounding point. 06 3-2 ant adaptive notch threshold level. sets the adaptive notch threshold. 06 1 ysel adaptive notch select. selects adaptive notch filter response. 06 0 notch notch enable. adaptive notch filter anf3 selected when high and anen is high, non-adaptive notch filter selected when high and anen is low. function may be overridden by xsf (reg 0e, bits 5-4). anr function 0 round to 10 bits 1 round to 8 bits ant function 00 magnitude difference less than 32 01 magnitude difference less than 24 10 magnitude difference less than 16 11 magnitude difference less than 8 ysel function 0 adaptive notch response anf1 1 adaptive notch response anf2
tmc22x5ya product specification 16 preliminary information control register de?itions (continued) comb processor control (07) 76543210 ls1by ls1in ls2dly split bsfby bsfsel bsfmsb grsdly reg bit name description 07 7 ls1by line store 1 bypass. bypasses linestore 1 when high. 07 6 ls1in line store 1 input. selects the input of linestore 1: 07 5 ls2dly line store 2 delay. lstore2 uses sts to store 1h when low and uses vl to store sav to eav (or max count) when high. 07 4 split line store 2 delay. splits data through lstore2, 9 bits chroma and 7 bits luma when high (chroma combs) and 8 bits chroma and 8 bits luma when low (luma comb). 07 3 bsfby bandsplit filter bypass. bandsplit filter is bypassed when high. 07 2 bsfsel bandsplit filter select. selects the bandsplit filter to be used: 07 1 bsfmsb inverts msb of bandsplit filter. when high, inverts the msb of the input to the bandsplit filter. 07 0 grsdly delays input to grs decode. when high, delays the input to the grs extraction circuit by 1h. genlock only. mid-sync level (08) 76543210 mids reg bit name description 08 7-0 mids mid sync level. sets the mid point of syncs for the mixed sync separator, in the subcarrier locked mode. ls1in function 0 primary input 1 secondary input bsfsel function 0 select bandsplit filter response 1 1 select bandsplit filter response 2
product specification tmc22x5ya 17 preliminary information control register de?itions (continued) extended drs (09) 76543210 pckf vstd reg bit name description 09 7-4 pckf clock rate. 09 3-0 vstd video standard. selects the video standard. pckf function 0000 13.50 mhz 0001 reserved 0010 reserved 0011 reserved 0100 14.32 mhz 0101 17.73 mhz 0110 reserved 0111 reserved 1000 12.27 mhz 1001 14.75 mhz 1010 15.00 mhz 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved vstd function 0000 ntsc-m 0001 ntsc-eiaj 0010 reserved 0011 reserved 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 pal-b, g, h, i 1001 pal-m 1010 pal-n (argentina, paraguay, uruguay) 1011 pal-n (jamaica) 1100 reserved 1101 reserved 1110 reserved 1111 reserved
tmc22x5ya product specification 18 preliminary information control register de?itions (continued) notes: 1. to enable ?uper blacks?and disable syncs of the output simply set msen[1] high and the sync gain to zero. output control (0a) 76543210 op8b oplmt oplmt msen opcmsb ybal buren reg bit name description 0a 7 op8b output rounded to 8 bits. rounds the outputs to 8 bits when high. the two lsbs are set to zero. 0a 6-5 oplmt output limit select. sets the output format and limiters: 0a 4-3 msen mixed sync enable. sets composite sync output format: 0a 2 opcmsb chroma output msb invert. inverts the msb of the c b c r or chroma output when high. 0a 1 ybal luma color correction. setting this bit high forces the chroma to zero whenever the luma equals or exceeds the luma limit. 0a 0 buren output burst enable. when high, passes the burst through on the chroma channel. sets the burst region to zero when low. oplmt function 00 rgb output format limited to 4 to 1016 01 yc b c r output format y limited to 4 to 1016 c b c r limited to 504 10 rgb output format limited to 4 to 1016 11 yc b c r output format y limited to 64 to 940 c b c r limited to 448 msen function 00 no sync, & ?uper blacks?disabled 01 no sync, & ?uper blacks?disabled 10 sync on g/y output only, & ?uper blacks?enabled 11 sync on rgb outputs, & ?uper blacks?enabled
product specification tmc22x5ya 19 preliminary information control register de?itions (continued) output control (0b) 76543210 fmt422 cdec yuvt reserved drsen drsck reg bit name description 0b 7 fmt422 enables c b c r output mux. when high, multiplexes the c b and c r data onto the same data bus. the chroma or multiplexed c b c r output appears on the b/c b output. the r/c r output is forced low. 0b 6 cdec c b c r decimation enable. when high, the c b c r data are decimated to 0:2:2 in the output processor. 0b 5 yuvt enables d1 output. when high, enables 4:2:2 multiplexed yc b c r onto the r/c r data output with trs words inserted into the output data stream. the y data are still available on the g/y output and multiplexed c b c r is available on the b/u output. 0b 4-2 reserved reserved, set to zero. 0b 1 drsen drs output enable. when high, enables the drs onto the g/y output. 0b 0 drsck drs data rate. sets the drs output data rate. drsck function 0 embeds data bytes (8 bits) at pck clock rate 1 embeds data nibbles (4 bits) at pxck clock rate
tmc22x5ya product specification 20 preliminary information control register de?itions (continued) comb filter control (0c) 76543210 adapt yces ycsel comb reg bit name description 0c 7-6 adapt adaption mode. sets the 3-line comb filter adaption mode in ntsc. 0c 5 yces yc input error signal control. error signal control for yc input, luma comb. 0c 4 ycsel luma/chroma comb filter select. selects luma or chroma comb filter. 0c 3-0 comb comb filter architecture. adapt[1:0] function 00 adapts to best of 3 types of line based comb filters in ntsc only. 01 adapts to the best of two field or frame based comb filters in ntsc only. 10 3 line (tap) comb only. never adapts to a 2 line (tap) filter. the higher set of comb filter error signals are sent to the xlut. ntsc or pal comb filter. 11 adapts to best of two 3 line chroma comb filters in pal only. yces function 0 lpf and hpf error signal, between (0h & 1h) or (1h & 2h) in ntsc or between (0h & 2h) in pal,are sent to xlut 1 lpf error signal, between (0h & 1h) and (1h & 2h) in ntsc or between (0h & 2h) in pal, are sent to xlut ycsel function 0 chroma comb filter 1 luma comb filter comb function yc or composite comb ?ter architectures 0000 pal or ntsc 3 line comb 0001 ntsc 3 line comb (0h & 1h) 0010 ntsc 3 line comb (1h & 2h) 0011 ntsc 2 line comb (0h & 1h) 0100 ntsc (2 line) field comb 0101 ntsc or pal field comb 0110 ntsc (2 line) frame comb 0111 ntsc frame comb d1 comb ?ter architectures 1000 3 line comb 1001 3 line comb (0h & 1h) 1010 3 line comb (1h & 2h) 1011 3 line comb (0h & 2h) 1100 (2 line) field comb 1101 field or 2 line (0h & 1h) comb 1110 (2 line) frame comb 1111 frame comb
product specification tmc22x5ya 21 preliminary information control register de?itions (continued) comb filter control (0d) 76543210 cest cesg yesg cestby xfen fast ywby reg bit name description 0d 7-6 cest chroma error signal transform. 0d 5 cesg chroma error signal gain. 0d 4 yesg luma error signal gain. 0d 3 cestby chroma error signal bypass. when high, bypasses chroma error signal. 0d 2 xfen xlut filter enable. when high, enables the lpf on the xlut output. 0d 1 fast adaption speed select. when high, the 3 line comb filter selects between comb filter architectures on a pixel by pixel basis. when low, the selection is filtered. 0d 0 ywby luma weighting bypass. when high bypasses the luma fail weighting. cest video standard clock rate (mhz) 00 pal/ntsc 4*fsc & 13.5mhz 01 ntsc 12.27mhz 10 pal 14.75mhz 11 pal 15mhz cesg function 0 normal chroma fail signal levels 1 double the chroma error signal levels yesg function 0 normal luma fail signal levels 1 double the luma error signal levels
tmc22x5ya product specification 22 preliminary information control register de?itions (continued) comb filter control (0e) 76543210 xip xsf ymux cmux reg bit name description 0e 7-6 xip xlut input select. selects the comb fail signals presented to the xlut: 0e 5-4 xsf xlut special function. 0e 3-2 ymux y output select. output selection of luma 4:1 mux 0e 1-0 cmux c output select. output selection of chroma 4:1 mux xip[1:0] input to xlut 00 2 bits of phase error (x[7:6]), 3 bits of chroma (x[5:3]) and luma magnitude error (x[3:0]). 01 4 bits of chroma (x[7:4]) and luma magnitude error (x[3:0]). 10 3 bits of phase error (x[7:5]), 3 bits of chroma magnitude error (x[4:2]), and 2 bits of luma magnitude error (x[1:0]). 11 4 bits of phase error (x[7:4]) and chroma magnitude error (x[3:0]). xsf luma chroma 00 comb simple 01 simple comb 10 flat with notch simple 11 flat with notch comb ymux output 00 comb 01 flat - comb 10 flat 11 simple cmux output 00 comb 01 flat - comb 10 flat 11 simple
product specification tmc22x5ya 23 preliminary information control register de?itions (continued) comb filter control (0f) 76543210 reserved cat dces ipcf yccomp sync reg bit name description 0f 7 reserved reserved, set to zero. 0f 6-5 cat adaption threshold. fixes threshold at which different comb filters are selected. 0f 4 dces d1 c b c r error signal. when set low for d1 chroma comb filters: a) in 3 line comb filter architectures, the magnitude error between the component data for that pixel selects the 3 line comb or adapts to a 2 line comb. on a ? b pixel?the error signal selected on pixel (x+4) is sent to the xlut with the magnitude difference between ? r pixels? on the same pair of lines, but from pixel (x+3). likewise on a ? r pixel?the error signal selected on pixel (x+5) is sent to the xlut with the magnitude difference between ? b pixels?on the same lines but from pixel (x+4). b) in 2 line comb filters the magnitude differences between the same pair of lines is always sent to the xlut, on a ? b pixel?the error from the preceding ? r pixel?is used and on a ? r pixel?the preceding ? b pixel?would be used. when set high for d1 chroma filters: this is used for 3 line comb filter architecture that are inhibited from adapting to 2 line comb filter architectures. the input to the xlut is the magnitude error in c r between (0h & 1h) and (1h & 2h) on ? r pixels?and the magnitude error between (0h & 1h) and (1h & 2h) on ? b pixels? 0f 3-2 ipcf comb filter input select. selects primary inputs to the comb filter. 0f 1 yccomp yc or composite input select. selects yc inputs when high and composite inputs when low. 0f 0 sync sync processor select. the syncs are obtained by a lpf when high and by the comb filter when low. sync pulse generator (10) 76543210 sts 7 sts 6 sts 5 sts 4 sts 3 sts 2 sts 1 sts 0 reg bit name description 10 7-0 sts 7-0 sync to sync 8 lsbs. bottom 8 bits of the number of pixels between sync pulses. 0 0 1 1 0 1 0 1 5% of max error 15% of max error 25% of max error 50% of max error ipcf function 0 0 0 1 1 0 1 1 flat video lpf output hpf output reserved
tmc22x5ya product specification 24 preliminary information control register de?itions (continued) sync pulse generator (11) 76543210 stb reg bit name description 11 7-0 stb sync to burst. controls the number of pixels from sync to burst. this signal starts the burst sample and hold. in sc mode, subtract 25 from the desired delay to generate this value. sync pulse generator (12) 76543210 btv reg bit name description 12 7-0 btv burst to video. controls the number of pixels from stb to the start of active video. sync pulse generator (13) 76543210 av 7 av 6 av 5 av 4 av 3 av 2 av 1 av 0 reg bit name description 13 7-0 av 7-0 active video line 8 lsbs. bottom 8 bits of the number of pixels during the active video line. sync pulse generator (14) 76543210 reserved av 9 av 8 reserved sts 10 sts 9 sts 8 reg bit name description 14 7-6 reserved reserved, set to zero. 14 5-4 av 9-8 active video line 2 msbs. two most significant bits of av. 14 3 reserved reserved, set to zero. 14 2-0 sts 10-8 sync to sync 3 msbs. three most significant bits of sts.
product specification tmc22x5ya 25 preliminary information control register de?itions (continued) sync pulse generator (15) 76543210 reserved vindo vdiv vdov reg bit name description 15 7 reserved reserved, set to zero. 15 6-2 vindo number of lines in vertical window. the number of lines (0 to 31) after the last eq pulse that the decoder passes through the vertical interval window. 15 1 vdiv action inside vindo. the vertical data inside the `vindo' is passed through a simple decoder when low, or is passed unprocessed on the luma channel with the chroma channel set to zero when high. 15 0 vdov action outside vindo. the vertical data after the `vindo' and before the end of vertical blanking is blanked (yuv = 0) when low, or passed through the simple decoder when high. sync pulse generator (16) 76543210 reserved nfdly spgip msip reg bit name description 16 7-6 reserved reserved, set to zero. 16 5-4 nfdly new field detect delay. ntsc frame detect delay: 16 3-2 spgip spg input select. selects the input to the sync pulse generator: 16 1 msip mixed sync separator input. set high for external videob reference or low for output of low pass filter. 16 0 smo state machine offset. set high for a 1h offset and low for a 0h offset. nfdly function 00 pixel count = 0 01 pixel count = 1 10 pixel count = 2 11 pixel count = 3 spgip input 00 external hsync and vsync 01 digitized sync (subcarrier mode) 10 trs words embedded in the d1 data stream 11 trs words embedded in the d2 data stream
tmc22x5ya product specification 26 preliminary information control register de?itions (continued) buffered register set 0 (17) active when buffer pin set low. 76543210 sg0 7 sg0 6 sg0 5 sg0 4 sg0 3 sg0 2 sg0 1 sg0 0 reg bit name description 17 7-0 sg0 7-0 msync gain, 8 lsbs. bottom 8 bits of mixed sync scalar lsb = 1/256 buffered register set 0 (18) active when buffer pin set low. 76543210 yg0 7 yg0 6 yg0 5 yg0 4 yg0 3 yg0 2 yg0 1 yg0 0 reg bit name description 18 7-0 yg0 7-0 y gain, 8 lsbs. bottom 8 bits of the luma gain lsb = 1/256 buffered register set 0 (19) active when buffer pin set low. 76543210 ug0 7 ug0 6 ug0 5 ug0 4 ug0 3 ug0 2 ug0 1 ug0 0 reg bit name description 19 7-0 ug0 7-0 u gain, 8 lsbs. bottom 8 bits of the u gain lsb = 1/256 buffered register set 0 (1a) active when buffer pin set low. 76543210 vg0 7 vg0 6 vg0 5 vg0 4 vg0 3 vg0 2 vg0 1 vg0 0 reg bit name description 1a 7-0 vg0 7-0 v gain, 8 lsbs. bottom 8 bits of the v gain lsb = 1/256 buffered register set 0 (1b) active when buffer pin set low. 76543210 yg0 9 yg0 8 ug0 10 ug0 9 ug0 8 reserved vg0 9 vg0 8 reg bit name description 1b 7-6 yg0 9-8 y gain, 2 msb. top 2 bits of the y gain. msb = 2 1b 5-3 ug0 10-8 u gain, 3 msbs. top 3 bits of the u gain. msb = 4 1b 2 reserved reserved, set to zero. 1b 1-0 vg0 9-8 v gain, 2 msbs. top 2 bits of the v gain. msb = 2
product specification tmc22x5ya 27 preliminary information control register de?itions (continued) buffered register set 0 (1c) active when buffer pin set low. 76543210 yoff0 7 yoff0 6 yoff0 5 yoff0 4 yoff0 3 yoff0 2 yoff0 1 yoff0 0 reg bit name description 1c 7-0 yoff0 7-0 y offset, 8 lsbs. bottom 8 bits of luma or rgb offset buffered register set 0 (1d) active when buffer pin set low. 76543210 reserved yoff0 8 sg0 9 sg0 8 reg bit name description 1d 7-3 reserved reserved, set to zero. 1d 2 yoff0 8 y offset, msb. msb of yoff 1d 1-0 sg0 9-8 msync gain, 2 msbs. top 2 bits of mixed sync scalar. msb = 2 buffered register set 0 (1e) active when buffer pin set low. 76543210 sysph0 6 sysph0 5 sysph0 4 sysph0 3 sysph0 2 sysph0 1 sysph0 0 vaxis0 reg bit name description 1e 7-1 sysph0 6-0 7 lsbs of phase offset. bottom 7 bits of the 15 bit system phase offset 1e 0 vaxis0 v axis flip. flips the sign of the v axis when high. buffered register set 0 (1f) active when buffer pin set low. 76543210 sysph0 14 sysph0 13 sysph0 12 sysph0 11 sysph0 10 sysph0 9 sysph0 8 sysph0 7 reg bit name description 1f 7-0 sysph0 14-7 8 msbs of phase offset. top 8 bits of 15 bit system phase offset. normalized subcarrier frequency (20) 76543210 fsc 3 fsc 2 fsc 1 fsc 0 reserved reg bit name description 20 7-4 fsc 3-0 bottom 4 bits of fsc. bottom 4 bits of the 28 bit subcarrier seed 20 3-0 reserved reserved, set to zero.
tmc22x5ya product specification 28 preliminary information control register de?itions (continued) normalized subcarrier frequency (21) 76543210 fsc 11 fsc 10 fsc 9 fsc 8 fsc 7 fsc 6 fsc 5 fsc 4 reg bit name description 21 7-0 fsc 11-4 lower 8 bits of fsc. lower 8 bits of the 28 bit subcarrier seed normalized subcarrier frequency (22) 76543210 fsc 19 fsc 18 fsc 17 fsc 16 fsc 15 fsc 14 fsc 13 fsc 12 reg bit name description 22 7-0 fsc 19-12 middle 8 bits of fsc. middle 8 bits of the 28 bit subcarrier seed normalized subcarrier frequency (23) 76543210 fsc 27 fsc 26 fsc 25 fsc 24 fsc 23 fsc 22 fsc 21 fsc 20 reg bit name description 23 7-0 fsc 27-20 top 8 bits of fsc. top 8 bits of the 28 bit subcarrier seed
product specification tmc22x5ya 29 preliminary information control register de?itions (continued) normalized subcarrier frequency (24) 76543210 clmpen pflten clpsel 1-0 clpby clpof 2-0 reg bit name description 24 7 drefsel decoder reference signal select. when high, enables a negative going clamp pulse on the dref pin. the position of the clamp pulse is controlled by register 24. when low the dref pin is high during the active video portion of each line and low during the horizontal and vertical blanking intervals. 24 6 pfltby phase error filter bypass. when high, no filtering is done on the phase error signals for the comb filter adapter. when low, the filter is enabled. 24 5-4 clpsel 1-0 internal black level clamp selection. 24 3 vclpen vertical clamp filter enable. when low, vertical clamp filter is disabled. when high, vertical clamp filter is enabled. 24 2-0 band 2-0 clamp guard band. when an error value between two consecutive lines black level is less than the guard band, it does not effect the filtered black level. normalized subcarrier frequency (25) 76543210 cpdly 7-0 reg bit name description 25 7-0 cpdly 7-0 clamp pulse delay. controls the number of clock cycles from hsync before the 0.5 m sec clamp pulse is output to the avout pin. this option is only enabled when register 24 bit 7 is set high. clmp[1:0] function 00 clamp disabled, black level set to 240 01 clamp disabled, black level set to 256 10 clamp enabled, use delayed videob input as reference 11 clamp enabled, use lpf as reference bands[2:0] function 000 no guard band 001 error value < 2 010 error value < 4 011 error value < 6 100 error value < 8 101 error value < 10 110 error value < 12 111 error value < 15
tmc22x5ya product specification 30 preliminary information control register definitions (continued) output format control (26) 76543210 reserved ldvio opcks dpcen dpc reg bit name description 26 7-6 reserved reserved, set to zero. 26 5 ldvio ldv clock select. ldv is an output when low and an input when high 26 4 opcks output clock select. the output data are clocked by the clock pin when low and by the ldv pin when high. 26 3 dpcen dpc enable. when high on the tmc22153a, the decoder product code is enabled: a value written into dpc determines the decoder product emulated by the tmc22153a. in all other versions of the decoder, dpc is read-only, and returns the code of the particular encoder version installed. 26 2-0 dpc decoder product code read/write in the tmc22153a only. read-only in all other devices. buffered register set 1 (27) active when buffer pin set high. 76543210 sg1 7 sg1 6 sg1 5 sg1 4 sg1 3 sg1 2 sg1 1 sg1 0 reg bit name description 27 7-0 sg1 7-0 msync gain, 8 lsbs. bottom 8 bits of the mixed sync scalar lsb = 1/256 buffered register set 1 (28) active when buffer pin set high. 76543210 yg1 7 yg1 6 yg1 5 yg1 4 yg1 3 yg1 2 yg1 1 yg1 0 reg bit name description 28 7-0 yg1 7-0 y gain, 8 lsbs. bottom 8 bits of the luma gain lsb = 1/256 dpc function 000 reserved 001 tmc22051a 010 TMC22052A 011 tmc22053a 100 reserved 101 tmc22151a 110 tmc22152a 111 tmc22153a
product specification tmc22x5ya 31 preliminary information control register de?itions (continued) buffered register set 1 (29) active when buffer pin set high. 76543210 ug1 7 ug1 6 ug1 5 ug1 4 ug1 3 ug1 2 ug1 1 ug1 0 reg bit name description 29 7-0 ug1 7-0 u gain, 8 lsbs. bottom 8 bits of the u gain lsb = 1/256 buffered register set 1 (2a) active when buffer pin set high. 76543210 vg1 7 vg1 6 vg1 5 vg1 4 vg1 3 vg1 2 vg1 1 vg1 0 reg bit name description 2a 7-0 vg1 7-0 v gain, 8 lsbs. bottom 8 bits of the v gain lsb = 1/256 buffered register set 1 (2b) active when buffer pin set high. 76543210 yg1 9 yg1 8 ug1 10 ug1 9 ug1 8 reserved vg1 9 vg1 8 reg bit name description 2b 7-6 yg1 9-8 y gain, 2 msbs. top 2 bits of the y gain msb = 2 2b 5-3 ug1 10-8 u gain, 3 msbs. top 3 bits of the u gain. msb = 4 2b 2 reserved reserved, set to zero 2b 1-0 vg1 9-8 v gain, 2 msbs. top 2 bits of the v gain msb = 2 buffered register set 1 (2c) active when buffer pin set high. 76543210 yoff1 7 yoff1 6 yoff1 5 yoff1 4 yoff1 3 yoff1 2 yoff1 1 yoff1 0 reg bit name description 2c 7-0 yoff1 7-0 y offset, 8 lsbs. bottom 8 bits of luma or rgb offset
tmc22x5ya product specification 32 preliminary information control register de?itions (continued) buffered register set 1 (2d) active when buffer pin set high. 76543210 reserved yoff1 8 sg1 9 sg1 8 reg bit name description 2d 7-3 reserved reserved, set to zero. 2d 2 yoff1 8 y offset, msb. msb of yoff 2d 1-0 sg1 9,8 msync gain, 2 msbs. top 2 bits of mixed sync scalar msb = 2 buffered register set 1 (2e) active when buffer pin set high. 76543210 sysph1 6 sysph1 5 sysph1 4 sysph1 3 sysph1 2 sysph1 1 sysph1 0 vaxiso reg bit name description 2e 7-1 sysph1 6-0 7 lsbs of phase offset. bottom 7 bits of the 15 bit system phase offset 2e 0 vaxis1 v axis flip. flips the sign of the v axis when high. buffered register set 1 (2f) active when buffer pin set high. 76543210 sysph1 14 sysph1 13 sysph1 12 sysph1 11 sysph1 10 sysph1 9 sysph1 8 sysph1 7 reg bit name description 2f 7-0 sysph1 14-7 8 msbs of phase offset. top 8 bits of 15 bit system phase offset.
product specification tmc22x5ya 33 preliminary information control register de?itions (continued) video measurement (30) 76543210 reserved lgf lgen lgext reserved pgg pgen pgext reg bit name description 30 7 reserved reserved, set to zero. 30 6 lgf line grab flag. set high when the decoder has grabbed a line, and must be reset low before another line can be grabbed. 30 5 lgen line grab enable. when high, the line grabber is used to freeze the contents of the line store, at the programmed line and field count. the phase and frequency of the frozen line are also stored from the drs, and are continually used to reset the dds, once per line, until lgf is set low. when lgen is low, the line freeze is disabled, the internal loops operate normally, and the line grab signal is used only to gate the pixel grab. 30 4 lgext ext line grab enable. the set pin is used to produce the line grabber pulse when high and the internal line decode is used when lgext is low. 30 3 reserved reserved, set to zero. 30 2 pgg pixel grab gate. when high the pixel grab is gated by the field and line grab signals to enable one pixel per four fields in ntsc and 8 field in pal to be grabbed. this function is disabled if pgen is set low. 30 1 pgen pixel grab enable. when high the 10 bit g/y, b/u, and r/v data, and the mixed sync and luma data after the comb filter, and the demodulated (b-y) and (r-y) color difference signals are grabbed once every line at the programmed pixel grab number. when low the contents of the pixel grab registers are held and the pixel grab pulse is ignored. 30 0 pgext ext pixel grab enable. the set pin is used to produce the pixel grab pulse when high and the internal pixel decode is used when pgext is low. video measurement (31) 76543210 pg 7 pg 6 pg 5 pg 4 pg 3 pg 2 pg 1 pg 0 reg bit name description 31 7-0 pg 7-0 pixel grab, 8 lsbs. bottom 8 bits of the pixel grab. video measurement (32) 76543210 lg 7 lg 6 lg 5 lg 4 lg 3 lg 2 lg 1 lg 0 reg bit name description 32 7-0 lg 7-0 line grab, 8 lsbs. bottom 8 bits of the line grab.
tmc22x5ya product specification 34 preliminary information control register de?itions (continued) registers 34-3c are read-only video measurement (33) 76543210 reserved fg lg 8 pg 10 pg 9 pg 8 reg bit name description 33 7 reserved reserved. 33 6-4 fg field grab number. field grab number 33 3 lg 8 msb of line grab. msb of line grab 33 2-0 pg 10-8 pixel grab, 3 msbs. 3 msbs of pixel grab register (34) 76543210 gy 9 gy 8 gy 7 gy 6 gy 5 gy 4 gy 3 gy 2 reg bit name description 34 7-0 gy 9-2 g/y grab, 8 msbs. top 8 bits of the "grabbed" g/y data register (35) 76543210 bu 9 bu 8 bu 7 bu 6 bu 5 bu 4 bu 3 bu 2 reg bit name description 35 7-0 bu 9-2 b/u grab, 8 msbs. top 8 bits of the "grabbed" b/u data register (36) 76543210 rv 9 rv 8 rv 7 rv 6 rv 5 rv 4 rv 3 rv 2 reg bit name description 36 7-0 rv 9-2 r/v grab, 8 msbs. top 8 bits of the "grabbed" r/v data register (37) 76543210 reserved gy 1 gy 0 bu 1 bu 0 rv 1 rv 0 reg bit name description 37 7-6 reserved reserved. 37 5-4 gy 1-0 g/y grab, 2 lsbs. bottom two bits of g/y data 37 3-2 bu 1-0 b/u grab, 2 lsbs. bottom two bits of b/u data 37 1-0 rv 1-0 r/v grab, 2 lsbs. bottom two bits of r/v data
product specification tmc22x5ya 35 preliminary information control register de?itions (continued) register (38) 76543210 y 9 y 8 y 7 y 6 y 5 y 4 y 3 y 2 reg bit name description 38 7-0 y 9-2 luma grab, 8 msbs. top 8 bits of the "grabbed" luma data after yproc register (39) 76543210 m 9 m 8 m 7 m 6 m 5 m 4 m 3 m 2 reg bit name description 39 7-0 m 9-2 msync grab, 8 msbs. top 8 bits of the "grabbed" mixed sync data after yproc register (3a) 76543210 u 9 u 8 u 7 u 6 u 5 u 4 u 3 u 2 reg bit name description 3a 7-0 u 9-2 u grab, 8 msbs. top 8 bits of the "grabbed" u data register (3b) 76543210 v 9 v 8 v 7 v 6 v 5 v 4 v 3 v 2 reg bit name description 3b 7-0 v 9-2 v grab, 8 msbs. top 8 bits of the "grabbed" v data register (3c) 76543210 y 1 y 0 m 1 m 0 u 1 u 0 v 1 v 0 reg bit name description 3c 7-6 y 1-0 luma grab, 2 lsbs. bottom 2 bits of luma data 3c 5-4 m 1-0 msync grab, 2 lsbs. bottom 2 bits of mixed sync data 3c 3-2 u 1-0 u grab, 2 lsbs. bottom 2 bits of u data 3c 1-0 v 1-0 v grab, 2 lsbs. bottom 2 bits of v data
tmc22x5ya product specification 36 preliminary information control register de?itions (continued) test control (3d-3e) 76543210 test reg bit name description 3d-3e 7-0 test must be set to zero. auto increment stops at 3f test control (3f) 76543210 vbit20 peddis ccden 5 ccden 4 ccden 3 ccden 2 ccden 1 ccden 0 reg bit name description 3f 7 vbit20 vbit20 enable. when high the v bit within embedded trs words is extended through line 20 for ntsc. when low, this v bit is high up to line 16 for ntsc. the pal operation is unaffected by this register bit. 3f 6 peddis pedestal disable. when high, pedestal is not removed from lines with lid = 00 to 06, lines 0 through 16 3f 5 ccden 5 closed caption data enable 5. when high, enables ntsc line 21 field 0 or pal line 22 field 0 to be passed ?lat? through the decoder, on the luminance channel and the pedestal removal will be disabled. 3f 4 ccden 4 closed caption data enable 4. when high, enables ntsc line 22 field 0 or pal line 23 field 0 to be passed ?lat? through the decoder, on the luminance channel and the pedestal removal will be disabled. 3f 3 ccden 3 closed caption data enable 3. when high, enables ntsc line 23 field 0 or pal line 24 field 0 to be passed ?lat? through the decoder, on the luminance channel and the pedestal removal will be disabled. 3f 2 ccden 2 closed caption data enable 2. when high, enables ntsc line 283 field 1 or pal line 334 field 1 to be passed ?lat? through the decoder, on the luminance channel and the pedestal removal will be disabled. 3f 1 ccden 1 closed caption data enable 1. when high, enables ntsc line 284 field 1 or pal line 335 field 1 to be passed ?lat? through the decoder, on the luminance channel and the pedestal removal will be disabled. 3f 0 ccden 0 closed caption data enable 0. when high, enables ntsc line 285 field 1 or pal line 336 field 1 to be passed ?lat? through the decoder, on the luminance channel and the pedestal removal will be disabled. status - read only (40) 76543210 ddsph reg bit name description 40 7-0 ddsph dds phase, 8 msbs. the top 8 bits of the sine data generated in the internal dds.
product specification tmc22x5ya 37 preliminary information control register de?itions (continued) status - read only (41) 76543210 linest bgst vact2 palodd vfly fgrab lgrab pgrab reg bit name description 41 7 linest pixel count reset. pixel count reset 41 6 bgst start of burst gate. start of burst gate 41 5 vact2 half line flag. half line flag 41 4 palodd pal ident. pal ident (low on ntsc lines) 41 3 vfly vertical count reset. vertical count reset 41 2 fgrab field grab. field grab 41 1 lgrab line grab. line grab 41 0 pgrab pixel grab. pixel grab status - read only (42) 76543210 fld vblk hblk lid reg bit name description 42 7 fld field ?g (f in d1 output). field flag (f in d1 output) 42 6 vblk vertical blanking (v in d1 output). vertical blanking (v in d1 output) 42 5 hblk horizontal blanking (h in d1 output). horizontal blanking (h in d1 output) 42 4-0 lid line identification. line identification status - read only (43) 76543210 ygo ygu ubo ubu vro vru reserved reg bit name description 43 7 ygo y/g overflow. y/g overflow 43 6 ygu y/g underflow. y/g underflow 43 5 ubo c b /b overflow. c b /b overflow 43 4 ubu c b /b underflow. c b /b underflow 43 3 vro c r /r overflow. c r /r overflow 43 2 vru c r /r underflow. c r /r underflow 43 1-0 reserved reserved.
tmc22x5ya product specification 38 preliminary information control register de?itions (continued) status - read only (44) 76543210 mono fperr reg bit name description 44 7 mono color kill flag. high when burst detected and low when monochrome signal is detected. 44 6-0 fperr frequency/phase error. top 7 bits of the modulo two pi frequency or phase error. reported once per line. status - read only (45) 76543210 drs reg bit name description 45 7-0 drs drs signal. the 8-bit decoder reference signal. status - read only (46) 76543210 partid reg bit name description 46 7-0 partid part family id. reads back the 8-bit part id number. read-only. returns cdh. status - read only (47) 76543210 revid reg bit name description 47 7-0 revid recoder revision number. revid tmc22x5y revision tmc22x5ya revision 05 f 06 g 10 a 11 b
product specification tmc22x5ya 39 preliminary information control register de?itions (continued) status - read only (48-4a) 76543210 reserved status - read only (4b) 76543210 pkill cfstat xop reg bit name description 4b 7 pkill phase kill from comb fail. phase kill from comb fail. 4b 6-5 cfstat comb ?ter status. comb filter status. 4b 4-0 xop xlut output. xlut output. status - read only (4c-ff) 76543210 reserved reg bit name description 4c-ff 7-0 reserved reserved. cfstat status 00 3 tap comb 01 3 tap [lower] comb 10 3-tap [upper] comb 11 2 tap comb
tmc22x5ya product specification 40 preliminary information decoder introduction all composite video decoders perform fundamentally the same operation. the ?st stage is to separate the luminance and chrominance. the second stage is to lock the internally generated sine and cosine waveforms to the burst on the decoded chrominance signal, demodulate, and then ?ter the chrominance signal to produce the color difference signals. the last stage either scales the luminance and color differ- ence signals, or converts them into red, green, and blue component video signals. these three stages are shown in figure 3. the complete separation of composite video signals into pure luminance (luma) and chrominance (chroma) signals is practically impossible, especially when the input source contains intraframe motion. therefore, the luminance (luma) signal will generally contain some high frequency chromi- nance, termed cross luma , and the chroma signal will contains some of the high frequency luma signal, centered around the subcarrier frequency, termed cross color . the degree of cross luma and cross color is directly propor- tional to the ?ter used for the yc separation, the picture con- tent, and the complexity of any post processing of the decoded signals. figure 3. fundamental decoder block diagram 65-22x5y-44 yc filter y y u vb r g c composite chrominance sin(wt) cos(wt+ f ) luminance matrix demodulation green red blue burst locked loop yc separation the relationship between the chrominance and luminance bandwidths is shown for both pal and ntsc in figure 4, wherein the shaded area denotes the part of the composite video frequency spectrum shared by both the chrominance and high frequency luminance signals. the luma notch and chroma bandpass technique for yc separation the simplest method of separating these chrominance and luminance signals, is to assume the chroma bandwidth is limited to a few hundred kilohertz around the subcarrier frequency. in this case a notch ?ter designed to remove just these frequencies from the composite video frequency spectrum provides the luma signal, while a bandpass ?ter figure 4. comparison of the frequency spectrum of ntsc and pal composite video signals chrominance subcarrier pal ntsc chrominance (& high frequency luminance) chrominance (& high frequency luminance) sound carrier center frequency chrominance subcarrier sound carrier center frequency frequency (mhz) frequency (mhz) amplitude (db) amplitude (db) luminance 11 2 2 3 3 4 4 4.5 56 -20 -3 0 -20 -3 0 luminance
product specification tmc22x5ya 41 preliminary information centered at the subcarrier frequency produces the chroma signal. this simple technique works well in pictures contain- ing large ?t areas of color, however this is rarely the case. if, as is generally true, the picture contains high frequency luma and chroma transitions, for example herring bone suit jackets, branches of trees, text, etc., cross color and cross luma artifacts are evident. the presence of cross color or cross luma is generally acceptable when viewing the decoded picture on a monitor from several feet, as would be the case in most homes on commercial television sets. however, these artifacts become increasingly dif?ult to process, or ignore, when the image is to be compressed or manipulated. in these cases more sophisticated methods of separating the luma and chroma signals, such as frame, ?ld, or line based comb ?ter decod- ers, are required. another important disadvantage of the ?uma notch ?ter and bandpass chroma?technique is that once a notch ?ter has been used on the luminance channel this portion of the lumi- nance frequency spectrum is lost. this effect becomes increasingly objectionable if the decoder component outputs are subsequently re-encoded into a composite video signal. comb filter architectures for yc separation a comb ?ter uses the relationship between the number of subcarrier cycles per line period, to cancel the chrominance signal over multiple line periods. this is shown for an ntsc two line comb ?ter in figure 6. in ntsc there a 227.5 sub- carrier cycles per line period, therefore the subcarrier can be canceled by simply adding two consecutive ?ld scan lines. in pal(b/i/ etc.) there are 283.7516 subcarrier cycles per line period, ignoring the 0.0016 cycle advance caused by the 25hz offset, the pal subcarrier can be canceled by adding the ?st and third line of three consecutive ?ld scan lines. due to the 270 degree advance, it is not possible to use infor- mation from consecutive ?ld lines without adding a pal modi?r. a pal modi?r produces a 90 degree phase shift in the chrominance signal by multiplying the chrominance signal by a signal at two times the subcarrier frequency that is phased locked to the subcarrier burst reference in the com- posite video waveform. in addition the pal modi?r inverts the v component of the chrominance signal. this document refers to line based comb decoders when discussing decoders that use inputs from sequential scan lines, i.e. lines from the same ?ld, ?ld based comb decoders when describing decoders that use inputs from sequential ?lds, and ?ally frame based comb decoders when examining decoders that use inputs from sequential frames. figure 6. composite line-based comb decoders the phase relationship of the quadrature modulated chromi- nance signal can also be represented as in figure 7. the three line comb based decoder is clearly biased towards 1h which illustrates the inherent one line delay through a 3 line comb, while a two line comb based decoder is biased towards 0h. in the following discussions a ?t color represents video of constant luma and chroma magnitude and phase. in ntsc, adding two adjacent lines of ?t color will cancel the chroma and leave the luma whereas subtracting two lines of ?t color will cancel the luma and leave the chroma. in a 3 line comb ?ter the ?t color on 0h and 2h is added to pro- vide the ?t color average before adding or subtracting from 1h. in pal, adding the ?t color from 0h and 2h will cancel the chroma and leave the luma while subtracting the ?t color from 0h and 2h will cancel the luma and leave the chroma. however, chroma generated in this manner has no simple delay = 1/t + 1/2 1/2t 1t 3/2t 2t 5/2t 3t 7/2t 4t 9/2t 5t 11/2t 6t frequency amplitude 1.0 figure 5. examples of notch and bandpass filters chrominance subcarrier notch filter bandpass filter chrominance subcarrier frequency f sc f sc frequency amplitude (db) amplitude (db) luminance -20 -3 0 -20 -3 0 chrominance (& high frequency luminance) chrominance (& high frequency luminance)
tmc22x5ya product specification 42 preliminary information phase relationship to the chroma on 1h. therefore normally 0h and 2h are added together to produce the average luma across 3 lines and this is then subtracted from 1h to produce the combed chroma. figure 7. chrominance vector rotation in pal and ntsc yc line-based comb filters the luminance and chrominance signals, are by de?ition, already separated for yc inputs. however, if the original source was composite, there is a distinct possibility that there is some residual luminance (cross color) in the chrominance signal and some residual chrominance (cross luma) in the luminance signal. it is therefore legitimate to treat these signals as if they were simply the output from bandsplit ?ters and process the luma and chroma signals accordingly. d1 line-based comb filters a d1 data stream consists of multiplexed y, c b and c r component data. if the original source was composite there maybe luminance (cross color) in c b c r and chrominance (cross luma) in y. in the ?st case any luminance that was passed through a demodulator along with the chroma to produce the baseband c b c r color difference signals would have the same characteristics as chroma. that is to say, the cross color would advance by 180 every line in ntsc and every 2 lines in pal. it is therefore possible to remove this cross color in a comb ?ter. in the latter case any chromi- nance that is still in the y data can obviously be removed in a comb ?ter as well. the original source for the d1 signal could also have been computer graphics. in this case, the comb ?ter can be used to remove the picture ?cker and convert the output to rgb. ntsc frame and field based decoders composite frame-based comb filters in ntsc the chrominance vectors advance by 180 degrees every line, therefore after 525 lines the 2 adjacent frame lines 0h and fr0h and the two consecutive ?ld lines fr0h and fr1h are 180 degrees apart. the ?t color on fr0h and fr1h can be added or subtracted to provide the luminance or chrominance to subtract from 0h. figure 8. chrominance vector rotation over 4 fields in ntsc composite field-based comb filters in ntsc ?ld based comb decoders, there is an external delay of 263 lines, therefore the 2 adjacent picture lines 0h and f0h and the two consecutive ?ld lines f0h and f1h are 180 degrees apart. the ?t color on f0h and f1h can be added or subtracted to provide the luminance or chromi- nance to subtract from 0h. pal field decoders composite, pal field comb filters in pal ?ld based comb decoders, there is an external delay of 312 lines, therefore the 2 adjacent picture lines 0h and f0h are 180 degrees apart. in ?lds 5, 6, 7, and 8 the u and v vectors are 180 degrees advanced from ?lds 1, 2, 3, and 4. figure 9. chrominance vector rotation over 4 fields in pal pal ntsc line no v u v u q q q q i i i v u v u v u n+1 n n+2 n+3 n+4 m m+1 m+2 m+3 2h 1h 0h 65-22x5y-48 field 0 0 0 0 0 1 1 1 1 line no q q q q q q q q q q q q q q q q i i i i i i i i i i i i i i i i 22 21 23 24 283 284 285 286 field 1 field 2 field 3 field 4 (1h) (0h) (f1h) (f0h) (fr1h) (fr0h) 65-22x5y-49 v v v u v v u u u v v v v u u v v u u u u v v v u u u u 24 23 25 26 336 337 338 65-22x5y-50 line no field 1 field 2 field 3 field 4 (0h) (f0h) (fr0h) (fr0h)
product specification tmc22x5ya 43 preliminary information the tmc22x5ya comb filter architecture the tmc22x5ya, when implementing a line based comb ?ter, has a core architecture as shown in figure 10. the con- cept of the complementary bandsplit ?ter is also observed in the complementary comb ?ter architecture. it is therefore possible to adapt between the complementary comb ?ter and bandsplit ?ter without throwing away any of the original composite video frequency spectrum. the ?st step in the complementary comb ?ter is to separate the high frequency luminance from the chrominance signal. this combed high frequency luma signal is shown as ycomb in figure 10. the second step is to produce an array of comb ?ter error signals that indicate the degree of con? dence that the ycomb signal is just the high frequency luma and not a combination of high frequency luma and chroma smeared over the number of lines used in the comb ?ter. the signal representing this degree of con?ence is termed ?? in figure 10. the last step is to provide a complementary cross fade between the ycomb signal and the output of the complementary bandsplit ?ter, shown as simple in figure 10. the flat signal is simply a delayed version of the input to the comb ?ter, therefore the sum of output1 and output2 will always be equal to the flat video input. the tmc22x53a comb ?ter architecture has three taps. these taps are three consecutive ?ld lines in a line based comb, three consecutive picture lines in a ?ld based comb, or lines that are one frame and one ?ld line apart in the frame based comb. in addition to these different inputs to the comb ?ter, ntsc and pal video signals comb over differ- ent taps in different architectures, as described in the comb ?ter introduction. the total internal pipeline latency is 1h + 40 pixels for 3 line comb ?ters, for all other comb ?ter and simple decoder architectures the pipeline latency is 40 pixels. figure 10. tmc22x5ya line based comb filter architecture input output1 output2 1h 1h bandsplit filters comb filter xlut xlut simple ycomb simple +/- {k * ycomb} k x +
tmc22x5ya product specification 44 preliminary information tmc22x5ya functional description input processor the input processor selects between the two external video sources on video a and video b. if the trs stripper or grs stacker is active, then the user must select the input with either the grs (in genlock mode) or with the embedded trs words as output va. if the input data are separate luma and chroma or y and c b c r data the input processor must be programmed to put the chrominance or c b c r onto output vb and the luminance or y onto va. to ensure that the chrominance data or the c b c r data are in twos complement arithmetic format, the register bit msbi inverts the msb of the db input. for composite inputs, the ipcmsb register bit should be set low, as the abmux register bit is used to select the input(s) to the comb ?ter. bandsplit filter (bsf) in its simple mode of operation, the tmc22x5ya uses a complementary bandsplit ?ter, instead of a notch ?ter for the luma and a bandpass for the chroma. the notch and bandpass ?ter technique, removes frequency bands from the composite video spectrum which can never be retrieved. the complementary bandsplit ?ter technique, shown in figure 12, allows the decoded component video signals to be re-encoded into a composite video signal with the minimum of losses to the composite video spectrum. figure 12. complementary bandsplit filter the complementary bandsplit ?ter separates the base band composite video into two bands by passing it through a low pass ?ter and subtracting the low pass (luma) data from the composite video to produce the high pass (chroma) data. as the base bandwidths and subcarrier frequencies of the differ- ent ntsc and pal video formats are so different, and the decoder has to be capable of working over a large frequency range, it is necessary to provide two low pass ?ters. these ?ters are selectable by the bsfsel register bit and are inde- pendent of the video standard. a comparison of the different data rates to normalized subcarrier frequencies is provided in table 2. the complementary bandsplit low pass frequency response is shown in figure 13 and figure 14. lpf input 65-22x5y-53 lpf output hpf output figure 11. input processor icpmsb abmux cksel tblk tden ip8b ipmux x trs stripper (d1/d2/d3) and grs stacker (tmc22071) msb 2:2 mux 2:2 mux invert va vb da db videoa videob primary data to comb filter secondary data to comb filter input processor control register msb lsb 65-22x5y-52
product specification tmc22x5ya 45 preliminary information comb filter input the inputs to the comb ?ter are selected from either the high frequency outputs of the bandsplit ?ters, if using a chroma comb ?ter, or the full composite waveforms when imple- menting a luma comb. the two sets of high and low fre- quency signals from the bandsplit ?ters are used for both the luma and chroma simple signals, and in the generation of the comb fail signals. these signals are denoted xhl, xhh, and xhf where l denotes the low frequency portion of the signal, h the high frequency portion of the signal and f the full frequency spectrum of the input signal from line x; and are shown in figure 15. table 2. normalized subcarrier frequency as a function of pixel data rates pixel rate (mhz) f sc (mhz) normalized f sc comments 12.27 3.57954545 0.2917 ntsc square pixel rate 13.50 3.57954545 0.2652 ntsc d1 pixel rate 13.50 4.43361875 0.3284 pal-i d1 pixel rate 14.32 3.57954545 0.2500 ntsc four times subcarrier (d2/d3) 14.75 4.43361875 0.3006 pal-i square pixel rate 15.00 4.43361875 0.2956 pal-i square pixel rate 17.73 4.43361875 0.2500 pal-i four times subcarrier (d2/d3) 13.5 3.57561149 0.2649 pal-m d1 pixel rate 13.5 3.58205625 0.2653 pal-n d1 pixel rate 14.30 3.57561149 0.2500 pal-m four times subcarrier (d2/d3) figure 13. bandsplit filter, full frequency response figure 14. bandsplit filter, passband response -70 -60 -50 -40 -30 -20 -10 0 0.00 0.10 0.20 0.30 0.40 0.50 normalized frequency attenuation (db) 65-22x5y-54 bandsplit filter 1 bandsplit filter 2 -6 -5 -4 -3 -2 -1 0 1 0.00 0.05 0.10 0.15 normalized frequency attenuation (db) 65-22x5y-55 bandsplit filter 1 bandsplit filter 2
tmc22x5ya product specification 46 preliminary information figure 15. block diagram of comb filter input the primary and secondary inputs are selected within the input processor. the primary input is normally the undelayed composite video signal in line, ?ld, and frame based comb ?ters or either the luma or chroma channel when processing yc or d1 signals. the secondary provides the ?ld or frame delayed composite input for ?ld and frame based comb ?ters and the chroma or luma channel when processing yc or d1 signals. when implementing a line based comb ?ter the outputs of 1h bandsplit ?ter, ie 1hh, 1hl, are delayed through the second line store, lstore2. the number of bits delayed is dependent upon the type of comb ?ter being implemented. for chroma comb ?ters all the bits of the 1hh signal are delayed, as this information supplies the outer tap of the chroma comb ?ter, while only the upper bits of 1hl are delayed as this data is used only in the generation of the luma error signals. in the case of luma combs an equal number of bits of the 1hh and 1hl signals are delayed and summed together to produce the 2hf signal for the outer tap of the luma comb ?ter. the con?uration of lstore2 is determined by the split register bit. it is important to note that when implementing a ?ld or frame based comb ?ter the secondary input must be selected by setting the lsin register bit high, and the ?st line store, lstore1, must be bypassed by setting the ls1by register bit high. for yc and d1 processing the secondary input bypasses the comb ?ter completely and provides the videob signal input the 3:1 multiplexer used to select the flat signal, see figure 16. lpf lpf delay 2:1 mux 2:1 mux 2:1 mux 2:1 mux lstore1 [9:0] lstore2 2hh lstore2 2hx lstore2 2hl 0hf 0hl 0hh 1hf 1hl 1hh 2hh 2hf 2hl 65-22x5y-56 videob + primary input secondary input bsfsel bsfsel ls1in ls1by 1hh 1hh (lsbs) 1hl split 1hl (lsbs)
product specification tmc22x5ya 47 preliminary information adaptive comb filter the ipcf[1:0] register bits select the inputs to the adaptive comb ?ter, this would normally be xhh for chroma combs, xhf for luma combs, and xhl if the luminance signal was to be sampled dropped on the output of the tmc22x5ya. the gaussian ?ters in the sample drop mode already limit the chrominance bandwidth to 1.3mhz allowing a [2:1:1] data format on the output, with the luminance signal having been vertically ?tered by a ?ed 3 line comb ?ter. the simp selection bit is an internally generated signal based upon the comb ?ter selected. if a 3 line chroma, luma, or d1 comb ?ter is selected, due to the internal 1h delay inherent with this type of comb ?ter, the 1hl and 1hh signals are selected for the respective luma and chroma simple data signals. when any other type of comb ?ter is selected 0hl and 0hh are selected. the dlyf selection bit is also internally generated from the type of comb ?ter selected and whether or not the input is in either the yc or y & cbcr (ie d1 input) data formats. the videob data is always selected when the yccomp register bit is high, ie for yc inputs. the selection of 1hf or 0hf depends upon the simp selection bit only when the yccomp register bit is low. therefore, when yccomp is low and 0hx is selected by simp then 0hf is selected for the flat signal, and when 1hx is selected by simp then 1hf is selected for the flat signal. this ensures that the flat and simple data selected for any comb ?ter is delayed by the same amount as the data processed through the comb ?ter to produce the comb output. the ?al selection is the output required for the combed luminance and chrominance data. the output selection can be simple , comb , flat-comb , or flat . generally comb is selected based upon whether a luma or chroma comb was selected and the complementary output selects flat-comb . in the yc and y & cbcr data modes the flat signal selects the secondary data and simple or comb can be used to select the primary signal. in these modes the bandsplit ?ter can be bypassed or used to remove low fre- quency noise from the chrominance signal if chroma was selected as the primary signal. figure 16. signal flow around the adaptive comb filter. simp ipcf[1:0] ohf ohh ohl 1hf 1hh 1hl 2hf 2hh 2hl videob ipcf[1:0] ymux[1:0] y data c data 65-22x5y-57 cmux[1:0] adaptive comb filter ipcf[1:0] simp a b c d a a: comb b: simple c: flat - comb d: flat b c d dlyf 2:1 mux 2:1 mux 3:1 mux 3:1 mux 3:1 mux 3:1 mux 4:1 mux 4:1 mux
tmc22x5ya product specification 48 preliminary information the comb ?ter architecture performs chrominance or lumi- nance comb ?tering on pal or ntsc video signals, by implementing one of sixteen independent chroma and luma comb ?ter algorithms. the highest level of the adaptive comb ?ter con?uration is determined by the sta[3:0] register bits as shown in table 3. table 3. comb filter architecture the comb signal can be produced in two ways. the ?st method uses the comb fail detection circuits to select one of several comb ?ter architectures. these comb ?ter architec- tures weight the three lines by varying degrees depending upon the degree of picture correlation between the inputs to the comb ?ter. the simple example in table 4 shows how this process works, in which upper denotes error compari- sons between the two lines stores and lower denotes error comparisons between the input and the ?st line store. the 0h, 1h, and 2h terms used in the mathematical description of the comb ?ter selection refer to the position with respect to the internal line stores. the 0h term is the undelayed input, 1h is the output of line store 1, and 2h is the output of line store 2. in this example a 3 line comb is implemented when in the ?t areas of blue or yellow. however, when a difference between the inputs is detected the 3 line comb ?ter adapts to the 2 line comb ?ter whose inputs have the smallest differ- ence. this illustrated on line n+4, at which time the comb ?ter adapts to inputs from 1h (blue) and 2h (blue) and ignores the 0h (yellow) inputs. in cases where there is a difference between all inputs to the comb ?ter, a 3 line comb ?ter is selected and the highest set of comb fail signals are sent to the xlut input logic. this technique would work well if pictures only contained vertical transitions, which is obviously not the case. there- fore the weighting of these comb ?ter taps, (0h, 1h, and 2h), are rarely just the simple ratios shown in table 4. it is worth noting that comb ?ters that use an even number of lines in the comb ?ter architecture produce chrominance and luminance signals that are vertically offset by one pic- ture line, i.e. in the middle of the even number of lines used in the comb ?ter input. while comb ?ters that use an odd number of lines, in the comb ?ter architecture, the chromi- nance and luminance produced is referenced to the center, i.e. the middle line, of the comb ?ter. this approach can consequentially cause aliasing in decoding composite video signals containing high frequency diagonal transitions. the fast register bit, when set low, ?ters the comb ?ter selection to decrease the sensitivity of the adaption algo- rithm. the second method completely disables the adaption between different comb ?ters, by setting the adapt[1:0] register bits accordingly, see table 5. sta[3:0] comb filter description 0 yc or composite, pal or ntsc, 3 line comb 1 yc or composite, ntsc, 3 line comb (0h & 1h) 2 yc or composite, ntsc, 3 line comb (1h & 2h) 3 yc or composite, ntsc, 2 line comb (0h & 1h) 4 yc or composite, ntsc, (2 line) field comb 5 yc or composite, ntsc or pal, field comb 6 yc or composite, ntsc, (2 line) frame comb 7 yc or composite, ntsc, frame comb 8 d1, y or c b c r , 3 line comb 9 d1, y or c b c r , 3 line comb (0h & 1h) 10 d1, y or c b c r , 3 line comb (1h & 2h) 11 d1, y or c b c r , 3 line comb (0h & 2h) 12 d1, y or c b c r , (2 line) field comb 13 d1, y or c b c r , field or 2 line comb (0h & 1h) 14 d1, y or c b c r , (2 line) frame comb 15 d1, y or c b c r , frame table 4. simple example of an adaptive comb filter architecture line no. input col- or error signals comb ?ter selection upper luma upper sat. upper hue lower luma lower sat. lower hue n+6 blue xxxxxx unknown without line n+7 n+5 blue 000000 [0h/4] + [1h/2] + [2h/4] n+4 blue 0 0 0 >0 0 180 [0] + [1h/2] + [2h/2] n+3 yellow >0 0 180 0 0 0 [0h/2] + [1h/2] + [0] n+2 yellow 000000 [0h/4] + [1h/2] + [2h/4] n+1 yellow 0 0 0 >0 >0 >0 [0] + [1h/2] + [2h/2] n black xxxxxx unknown without line n-1
product specification tmc22x5ya 49 preliminary information in either of these methods, the ? signal can be used to cross fade between the ycomb and the simple bandsplit signals. the resulting comb ?ter equation can be expressed as: combed luma = simple + (k * combed high frequency luma) combed chroma = simple - (k * combed high frequency luma) in the case of the chroma comb, the weighted combed high frequency luma is subtracted from the simple high pass ?- ter output to produce the combed chroma signal, and for luma comb ?ters the weighted combed high frequency luma is added to the simple low pass ?ter output to provide the combed luminance signal. comb fails the inputs to the comb ?ter are monitored to detect discon- tinuities that would cause the comb ?ter operation to fail. whenever a signi?ant failure is predicted, the comb ?ter architecture is modi?d and an error signal proportional to the discontinuity is produced. for ?t areas of color, it is a relatively simple to produce an error signal that switches between the outputs of the comb ?ter and the simple band split ?ter without visibly softening the picture horizontally or vertically. however, as horizontal frequencies increase during vertical transitions, so the decision for switching between the comb and simple bandsplit decoder becomes more complex. a line based comb ?ter can separate the luma and chroma signals from line repetitive composite video signals, with no loss of luma or chroma bandwidth. however, if there is a ver- tical transition, i.e. a change from one scan line to the next, as shown for a ntsc two line comb in figure 17, a comb fail occurs. the comb fail shown in figure 17, clearly illus- trates the resulting vertical smearing of the luma and chroma signals. in addition to the smearing, the resulting phase of the chrominance signal with respect to the burst can cause hue errors in the demodulated picture. in this example, the chrominance signal would be demodulated with a 180 degree phase error. unlike the ?imple?decoder technique any errors in the comb ?ter decoding produce components that if re-encoded will never reproduce the original compos- ite video waveform. it is therefore imperative that the num- ber and magnitude of comb fails be kept to its absolute minimum. this is not possible with non-adaptive comb ?ter architectures, and all vertical and diagonal transitions in the picture will cause irreversible picture degradation. for this reason, all the tmc22x5ya comb ?ter decoders implement an adaptive comb ?ter architecture. to aid in this decision making process, comprehensive comb fail signals are generated and fed to a user-programmable lookup table (xlut). the output of the lookup table pro- vides the control for the cross fade between the comb and simple bandsplit decoder. comb fail detection the traditional approach of using the low frequency data to look for vertical luma transitions, and rectifying the high frequency data to estimate vertical transitions in the chroma provides adequate comb fail detection. however, chroma signals that are equal in magnitude but 180 degrees apart in phase, which can also have a small difference in luma level, for example green and magenta, can produce undetected comb fails in the comb ?ter output. to overcome problems with simpler comb fail measurement techniques, the tmc22x5ya generates an array of patented comb fail and comb ?ter control signals. to produce these signals each input to the comb ?ter is passed through a sim- ple bandsplit decoder. this provides a luma signal from the low frequency portion of the comb ?ter input, and the hue (phase) and saturation (magnitude) from the high frequency portion of the comb ?ter input. these signals are compared and the differences in luma, hue, and saturation are used to determine the type of comb ?ter used to generate the ycomb signal and to provide the cross fade control signal ? . the ? signal can be weighted within the xlut lookup table, allowing the user to tailor the comb ?ter response to their system requirements. figure 17. example of a comb fail using a nstc two line comb filter 65-22x5y-58
tmc22x5ya product specification 50 preliminary information generation of the comb fail signals luma error signals the signals from the 3 low pass ?ters, 0hl, 1hl, and 2hl are subtracted from one another to produce an error signal proportional to the luma comb fail. the resulting signals (0hl - 1hl), produces lye, and either (1hl - 2hl) in ntsc or (0hl - 2hl) in pal produces uye . the lye and uye luma error signals are recti?d if negative. in cases where the luminance component is constant, the error will be zero. where the luminance goes from black to white over 2 lines, the error signal will go to its maximum value. the luma error signals can be doubled to facilitate inputs with low picture levels by setting the yesg register bit high. the resulting signal is clipped to ensure no over?w occurs hue and saturation error signals in the past, comb decoders have relied upon comparing the difference in chroma magnitude between two lines to deter- mine a comb fail. in fact, this chroma signal is normally the output of the high-pass or band-pass ?ter, and therefore con- tains all the high frequency luminance information as well. as this signal was never demodulated, the sign bit was immaterial and was used only to rectify the chroma signal. this allowed chroma signals which where equal in magni- tude but opposite in phase, and high frequency luminance signals, to fool the comb fail circuit. the tmc22x5ya uses a new, innovative approach to over- come this problem. to detect comb failures in the high- frequency portion of the video signal the outputs from the three high-pass ?ters, 0hh, 1hh, and 2hh, are passed through simple demodulators. the outputs from which provide the phase and magnitude of the in-phase and quadra- ture components of the high frequency data. these compo- nents are compared to determine the difference in phase and magnitude between 0h & 1h in all con?urations, lme and lpe , and between 1h & 2h in ntsc or 0h & 2h in pal, ume and upe . the magnitude error signals can be doubled to facilitate inputs with low picture levels by setting the cesg register bit high. the doubled magnitude error signals are limited to ensure no over?w occurs. the algorithm used to separate the quadrature components depends upon the relationship between the normalized sub- carrier frequency and the number of pixels per line. this algorithm is preset for either a ntsc/m or pal/i subcarrier frequency and a pixel data rate of 13.5mhz. it is therefore necessary to compensate for other pixel data rates by select- ing the appropriate default using the cest[1:0] register bits. picture correlation the degree of picture correlation depends upon the differ- ences between the uye, ume, and upe upper error signals and the lye, lme, and lpe lower error signals, and is mea- sured as a percentage of full scale error. in ?t ?lds of color you would have 0% error in picture correlation, however in sharp vertical transitions say between yellow and blue you would have large % errors between uye and lye and between upe and lpe , while there would be 0% error between ume and lme . adapting the comb filter in ntsc it is possible to switch from a 3 line comb to a 2 line comb, and then to a simple decoder output. the 3 line comb to 2 line comb switch can be disabled, forcing the 3 line comb to switch directly to simple. the switching between these two comb architectures is independent of the figure 18. generation of upper and lower comb fail signals luma comparison uye lye upe lpe ume lme yesg ywby cesg csetby cest[1:0] ohh ohl 65-22x57-59 1hl 2hl 1hh 2hh hue comparison saturation comparison chroma demodulation & rectangular to polar conversion
product specification tmc22x5ya 51 preliminary information mix signal, k. for 3-line y/c comb ?ters, an external 1h delay is required in the uncombed channel to compensate for the comb ?ter delay. this principle is equally true for ntsc frame and ?ld based comb decoders. the feature is not available for any of the pal comb ?ter architectures. the comb ?ter adaption threshold register bits cat[1:0] determine if 5%, 15%, 25%, or 50% errors in picture correla- tion is required to adapt the ntsc comb ?ter. in ntsc, due to the 180 degree advance in subcarrier phase per line, it is possible to switch between the 3 line comb and the choice of either the upper two line comb or the lower two line comb. if this switching occurs on a pixel by pixel basis the picture will contain vertical alias components. this artifact can be reduced by either setting the fast register bit low, which ?ters the comb ?ter selection, and/ or setting the cat[1:0] register bits to a higher percentage threshold. the comb ?ter adaption is further controlled by the adapt[1:0] register bit selection, when the comb[3:0] register bits select a 3 line comb. these bits control if the comb ?ter adapts from a 3 line comb to the best of the upper or lower 2 line combs, from a 3 line comb to just the lower 2 line comb, performs a ?ed 3 line comb, or implements a best of two 3 line combs in pal. if the comb[3:0] register bits select one of the 2 line comb ?ters, the adapt[1:0] register bits are ignored, and no adaption is implemented. the cfsel[1:0] signal, shown in figure 19, controls which comb ?ter is selected on a pixel by pixel basis, and can be externally monitored by reading cfstat[1:0] in register 4bh. table 5. adaption modes xlut the comb fail signals control both the comb ?ter adaption and the cross fade between the adaptive comb ?ter output ycomb and the simple bandsplit signal. which of the fail signals is fed to the xlut is determined by which comb ?ter is selected in ntsc. when a 3 line comb ?ter is selected, the larger set of error signals are sent to the xlut, when a upper 2 line comb is selected uye , ume , and upe error signals are selected, and when a lower two line comb ?ter is selected the lye , lme , and lpe error signals are selected. adapt[1:0] function 00 adapts to the best of 3 types of line based comb filters in ntsc only. 01 3 line (tap) comb always adapts to lower 2 line (tap) comb, when the 3 line (tap) comb fails. normally used with ntsc field and frame based comb filters. 10 3 line (tap) comb only. never adapts to a 2 line(tap) filter. the higher set of comb filter error signals are sent to the xlut. ntsc or pal comb filter. 11 adapts to best of two 3 line comb filters in pal only. figure 19. comb filter selection adapt[1:0] comb fail logic filter 2:1 mux ycsel 65-22x5y-60 cfsel[3:0] yerr perr merr fast sta[3:0] cat[1:0] uye lye upe lpe ume lme
tmc22x5ya product specification 52 preliminary information for pal comb ?ters the lye , lme , and lpe errors signals are always selected by default. in this way the error signals into the xlut always represent the comb ?ter being imple- mented. the resolution of the error signals selected is con- trolled by the xip[1:0] register bits as shown in table 6: xlut input selection. the position of these error signals on the xlut input address x[7:0] is also shown. the selected comb fail signals are translated by the user- programmed con?uration within the 256*5 xlut into the mix signal (k) which controls the 30 levels of cross-fade between the weighted comb ?ter and the band split ?ters. the 1 to 31 mix signal is modi?d on the input to the cross- fade to produce a 0 to 32 control signal, as shown in table 7. the special function assigned to k = 0 is programmed into the xsf[1:0] register bits, as shown in table 8. table 8. xlut special function definitions the ?lat with notch?selection passes the flat input through onto the luminance channel and selects the notch ?ter, centered at 0.25 of the normalized clock frequency. this mode is therefore only useful with inputs at 4*fsc or in cases when a notch at 0.25 of the normalized clock frequency is adequate for application. the xlut output, is fed through a bypassable low-pass ?ter klpf to avoid switching between comb and simple decoders on a pixel by pixel basis. when the special function is selected (k = 0) the input to the klpf is held and the ?ter is automatically bypassed. the output of the xlut can be externally monitored by reading xop[4:0] in register 4bh. table 6. xlut input selection xip[1:0] function 00 2 bits of phase error (x[7:6]), 3 bits of chroma (x[5:3]) and luma magnitude error (x[3:0]). 01 4 bits of chroma (x[7:4]) and luma magnitude error (x[3:0]). 10 3 bits of phase error (x[7:5]), 3 bits of chroma magnitude error (x[4:2]), and 2 bits of luma magnitude error (x[1:0]). 11 4 bits of phase error (x[7:4]) and chroma magnitude error (x[3:0]). table 7. xlut output function. xlut output k 0 special function (e.g. luma comb and hpf on chroma) 1 0 - 100% bandsplit 22 33 :: 16 16 - 50% bandsplit, 50% comb :: 29 29 30 30 31 32 - 100% comb kip 1-0 xlut special function selection yc 00 comb simple 01 simple comb 10 ?t with notch simple 11 ?t with notch comb table 7. xlut output function. (cont.) xlut output k figure 20. xlut input selection xlut xlut input select filter 2:1 mux 65-22x5y-61 k[4:0] xfen xip[1:0] x[7:0] yerr perr merr
product specification tmc22x5ya 53 preliminary information digital burst locked loop the digital burst locked loop provides sine and cosine signals which are phase locked to the incoming burst signal. these sine and cosine signals are used to demodulate the chromi- nance data, producing the u and v color-difference signals. the u data are phase-referenced to sin(wt) and the v data to cos(wt). the demodulated signal is passed through a low pass filter to remove signals at twice the subcarrier frequency. the magnitude of the u and v data within the demodulated burst signal provides the error signal which, after filtering, is used to adjust the frequency and/or phase of the subcarrier dds. the output of the subcarrier dds is translated into sine and cosine signals in rom-based lookup tables. the palodd signal is low on lines without the 180 degree phase advance in the modulated v signal, termed ntsc lines, and high for lines with the 180 degree phase advance, termed pal lines. this signal is used in the burst locked loop to advance the phase of the cosine table on pal lines. pal- odd is always low for ntsc. color kill counter the demodulated u and v components are compared to a programmable burst level threshold. if both the u and v data fall below this threshold, a color kill ?g is set high. the color kill counter is incremented once per line if the color kill ?g is high. if the count reaches 127 within one ?ld, the color kill circuit becomes active during the next ?ld group. when this occurs, the input video will be passed unaltered on the luminance channel and the color difference signals will be set to chroma black. the color kill signal remains active until a ?ld with less than 127 lines without burst is encountered, at which time, during the next vertical blanking period, the decoder is reset. the operation of the color kill logic can be monitored exter- nally by reading the mono register bit in register 44h. the mono bit is high for composite and yc video signals and low for monochrome signals. field flag, fld the fld signal is the lsb of the ?ld count fid 2-0 and is low for ?lds where the ?st vertical sync occurs in the ?st half of the line and is high for ?lds when it occurs in the second half of the line. this signal is synchronized with the frame and color frame ?gs in the fid generator. frame bit ntsc the middle bit (frame bit) of the ?ld count is determined, by the phase of the subcarrier on a given pixel and on a given line. the signal used to determine this is nfdet (new field detect), and occurs when the line count is zero and the pixel count is one of four programmable pixel positions, zero, one, two, or three. pal the frame bit in pal is detected through the bruch blanking sequence. the error signal control circuit generates a color kill ?g whenever a line is detected without a burst. it is therefore possible to compare this signal with speci? line idents to determine the ?ld sequence in both pal-i and pal-m. a set of speci? patterns determine the correct phase of fid 1 ; if any of these patterns is detected then fid 1 is forced to a known state and then ?wheels until the next ?ed pattern is detected. table 9. pal-b,g,h,i bruch blanking sequence the frame bit is low for frames 0 and 2 and high for frames 1 and 3. internal line # burst present internal frame # internal ?ld # 5 no 0 or 2 0 or 4 309 no 0 or 2 0 or 4 6 yes 0 or 2 1 or 5 309 no 0 or 2 1 or 5 5 yes 1 or 3 2 or 6 309 yes 1 or 3 2 or 6 6 no 1 or 3 3 or 7 309 yes 1 or 3 3 or 7 . figure 21. block diagram of digital burst locked loop chrominance burst locked loop gaussian lpf u data v data gaussian lpf sin(wt) 65-22x5y-62 cos(wt+ f )
tmc22x5ya product specification 54 preliminary information table 10. pal-m bruch blanking sequence the frame bit is low for frames 0 and 2 and high for frames 1 and 3. pal color frame bit the pal color frame bit is the msb of the field count, fid 2 . in ntsc this is always low, as ntsc has only a 4 field se- quence. for both pal-i and pal-m inputs, the pal color frame bit is determined in the same way the frame bit is de- termined in ntsc, by using the phase of the subcarrier on a given pixel and on a given line. hue control one of two programmable 16 bit system phase offsets can be added to the subcarrier oscillator between sav and eav. the selection is made by the buffer pin. this feature allows the user to change the picture hue on known frames without affecting the burst locked loop. system monitoring of the burst loop error the burst loop error signal is stored once per line in an 8 bit register that can be accessed over the microprocessor port. this allows the user to check for non-mathematical pal in- puts and to the change the decoder architecture from frame- based to line-based or simple decoder depending on this in- formation. demodulation low pass filter there are two different demodulation low pass ?ters that can be selected under software. for pal inputs with normal- ized subcarrier frequencies greater than 0.3 of the sampling frequency, it is recommended you use ?emodulator ?ter 2? to stop aliasing of the second harmonic of the demodulation chrominance signal and the baseband color difference sig- nals. gaussian ?ters are used for both demodulation ?ters as they have no negative coef?ients and therefore have no undershoots or overshoots which could cause in-band ringing. figure 22. gaussian low pass filters figure 23. gaussian lpf passband detail bypassing the chrominance demodulator the demodulation of the chrominance signal needs to be bypassed when the decoder is processing c b c r component data or when a yc output is required. the bypass operation is controlled by the dmodby register bit. bypassing the demodulation low pass filter the demodulation low pass ?ter needs to be bypassed when processing c b c r component data or when a yc output is required. the c b c r data can also be passed through the gaussian ?ter if the bandwidth needs to be reduced. the bypass operation is controlled by the gauby register bit. chrominance coring chrominance coring, when active, sets the lsbs of the chroma channel (below a programmable threshold) to zero. vmcr 5 operation when vmcr 5 is high, the decoder will grab one line of video in lstore1. this effectively removes the comb ?ter from the decoding process, and the comb ?ter output is forced to simple mode. internal line # burst present internal frame # internal ?ld # 7 no 0 or 2 0 or 4 258 yes 0 or 2 0 or 4 7 no 0 or 2 1 or 5 259 no 0 or 2 1 or 5 7 yes 1 or 3 2 or 6 258 no 1 or 3 2 or 6 7 yes 1 or 3 3 or 7 259 yes 1 or 3 3 or 7 -70 -60 -50 -40 -30 -20 -10 0 0.00 0.10 0.20 0.30 0.40 0.50 normalized frequency attenuation (db) 65-22x5y-63 demodulator filter 1 demodulator filter 2 -10 -8 -6 -4 -2 0 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 normalized frequency attenuation (db) 65-22x5y-64 demodulator filter 1 demodulator filter 2
product specification tmc22x5ya 55 preliminary information output processor figure 24. output processor block diagram clamp circuit a clamp pulse generated by the burst gate signal is used to grab either a sample of the low-pass-?tered luma during the video back porch, the signal on videob, or one of two internally generated levels. the selection is made by the clmp[1:0] register bits. table 11. blanking level selection the blanking level is subtracted from the decoded luma. if the sign is negative, the result is assumed to be mixed sync and is passed through a delay and into the sync gain stage within the output matrix. if the sign is positive, the result is assumed to be pure luma (blanking to peak white) and is fed to the pedestal removal circuit. pedestal removal the 8 bit programmable pedestal is subtracted from the pure luma signal. the negative super black signals are clipped to zero when register 0ah bit 4 is set low, or the super black signals are passed through the luma scalar when register 0ah bit 4 is high. clamp generator the tmc22x5ya has the unique option to output a negative going clamp pulse that is 0.5 m sec wide. this pulse can be output on the avout pin by placing a high on register 24 bit 7. the pulses position relative to hsync can be varied by register 25. this value is the number of pck clock cycles after an hsync that the pulse will be output to the pin. the clamp pulse can be used to control where an analog clamp circuit grabs the analog reference to establish the correct voltage level into the a/d. usually the clamp pulse is gener- ated on the back porch or duing the sync tip of a video line. adaptive notch filter the pal line-locked comb decoder can never provide perfect subcarrier cancellation due to the 25hz offset in the subcarrier frequency. this 25hz offset causes residual and phase modi?d subcarrier to be left on the luminance signal which can produce a visible dot crawl on ?t areas of color. however, for all comb ?ter structures, the quality of the comb depends on the quality of the sampling clock, as line to line clock jitter will also cause small phase changes between the inputs to the comb ?ter. it is therefore possible that ntsc comb decoders may also require some coring of the luma output. to meet the wide range of sample frequencies that the decoder must deal with two separate coring ?ters are selectable. the luma signal from the pedestal stripper is compared against the preceding pixel to detect the magnitude change between pixels. this magnitude difference will be almost zero for ?t areas of picture, and large for high frequency changes in the picture. the magnitude difference is com- pared to one of four programmable thresholds. the program- mable threshold is selected by the ant 1-0 register bits as shown in table 12. table 12. adaptive notch threshold control mixed sync 65-22x5y-65 sgx[9:0] x x x x x x ygx[9:0] yoff[8:0] adaptive luma notch filter ant[1:0] clmp[1:0] clamp circuit + + vclpen ped[7:0] y data videob lpf u data v data 256 240 ysel anen fixed (b-y) gain stage fixed (r-y) gain stage ugx[10:0] vgx[10:0] g/y data b/cb data r/cr data output formatter clmp[1:0] blanking selection 00 internal 240 level 01 internal 256 level 10 external videob input 11 internal lpf output ant 1-0 magnitude difference 00 less than 16 01 less than 12 10 less than 8 11 less than 4
tmc22x5ya product specification 56 preliminary information if either of the error signals indicates that the magnitude difference is above the programmed threshold, or if anen is low, the adaptive notch ?ter is bypassed. the output of the adaptive notch ?ter is rounded to 8 or 10 bits, or the luma data that bypasses the coring ?ter is truncated to 8 or 10 bits depending upon the coro register bit. figure 25. adaptive notch filters luma notch filter the simple luma notch ?ter is centered at 0.25 of normal- ized frequency, it therefore intended for use only in the sub- carrier mode (4 * fsc) and for limited use with 13.5mhz ntsc as the subcarrier sits at 0.265 of normalized fre- quency. the notch ?ter is enabled by setting the notch register bit high. figure 26. luminance notch filter matrix the magnitude of the decoded luminance and color differ- ence signals will vary, not only with the standard, but also with the input mode. for this reason the output matrix contains programmable multipliers, and not just ?ed scaling factors. the following sub sections explain the differ- ent scalar in the output matrix. the gain term in the y, mixed sync, u and v scalar is the same - only the weighting makes them different. the scalar are capable of independently providing 6db of gain if required. programmable u scalar the u scalar (ugx) provides the weighting required to produce (b-y) or c b from the demodulated u signal. hence (b-y) = ugx * u where ugx = gain / 0.493, and c b = ugx * u where ugx = (gain * 448) / umax ugx has a scaling range of 0 to (2047/256). programmable v scalar the v scalar (vgx) provides the weighting required to produce (r-y) or c r from the demodulated v signal. hence (r-y) = vgx * v where vgx = gain / 0.877, and c r = vgx * v where vgx = (gain * 448) / vmax vgx has a scaling range of 0 to (1023/256). programmable y scalar the y scalar (ygx) provides the scaling for the luminance signal if the output is yc b c r , or controls the magnitude of the rgb output along with the u scalar and v scalar. it is not possible to control the magnitude of the rgb signals inde- pendently. ygx has a scaling range of 0 to (1023/256). programmable ms scalar the sync scalar (sgx) provides the scaling for the sync signal if the output requires sync on rgb. the programmed sync scaling factor is used during the horizontal and vertical burst blanking periods. during the active lines, the luma scaling factor is used to allow scaling of ?uper blacks?etc., which will be passed down the mixed sync path because they fall below the clamp level. sgx has a scaling range of 0 to (1023/256). fixed (b-y) and (r-y) scalars these two scalars are zero when the output is yc b c r and provide the (b-y) and (r-y) weighting when the output is rgb. these are ?ed scaling factors and are derived from the following equations. (g-y) = - [(0.299/0.587) * (r-y)] - [(0.114/0.587) * (b-y)] or (g-y) = - [(1043/2048) * (r-y)] - [(398/2048) * (b-y)] -70 -60 -50 -40 -30 -20 -10 0 0.00 0.10 0.20 0.30 0.40 0.50 normalized frequency attenuation (db) 65-22x5y-09 adaptive notch filter 1 adaptive notch filter 2 adaptive notch filter 3 2 -70 -60 -50 -40 -30 -20 -10 0 0.00 0.10 0.20 0.30 0.40 0.50 normalized frequency attenuation (db) 65-22x5y-67
product specification tmc22x5ya 57 preliminary information y offset the 8 bit y offset adds any offset required in the y or rgb data outputs. for example 64 (16) for the 64 (16) to 940 (235) 10 bit (8 bit) 601 outputs. when the output is yc b c r this offset is applied to the luminance data only. the y offset also provides the blanking level for rgb outputs with syncs. matrix limiters the different limiters are listed below, 10 bit data is assumed. table 13. matrix limiters examples of output matrix operation from the smpte-170m speci?ation: yc b c r data ranges are: y data range is 64 to 940 (876) c b c r data ranges are 64 to 960 (+/- 448) matrix programming: ygx = (876 / 540) = 1 + (159/256) ugx = (448 / 236) = 1 + (230/256) vgx = (448 / 332) = 1 + (89/256) yoff = 64 ped = 44 pal digital composite input and rgb (0-1023) outputs: the nominal scaling factors are simply: ygx = 1023/572 = 1 + (202/256) ugx = (1023/572)*(1/0.492) = 3 + (163/256) vgx = (1023/572)*(1/0.877) = 2 + (10/256) yoff= 0 ped = 0 it is also possible with the architecture supplied to use the limiters on the output of the matrix to clip the output video deliberately by using a slightly larger gain than is required. the y_offset can achieve the same by setting its value to be one lsb less than the minimum clip level. buffer registers the buffer pin allows the user to externally switch between two sets of internal registers that have the same function. this register buffering allows the matrix gain, picture hue, and luma offset to be changed at a known time relative to the input data. registers 17 to 1d are selected when the buffer pin is low and registers 27 to 2d are selected when the buffer pin is high. if the msb of the decoder product code dpc 2 is low, an 8 bit decoder has been selected and the bottom 2 bits of registers 17 to 1a and 27 to 2a are forced to zero. lmt 1-0 comments 00 rgb output format, limited from 0 to 1023 01 yc b c r output format, y limited from 0 to 1023 and c b c r limited to +/- 511. 10 rgb output format, limited from 64 to 940 11 yc b c r output format, y limited from 64 to 940 and c b c r limited to +/- 448 color y u v white 584 0 0 yellow 523 -236 54 cyan 423 79 -332 green 361 -156 -278 magenta 267 156 278 red 205 -79 332 blue 105 236 -54 black 44 0 0 decoder output ccir 601 spec color y c b c r yc b c r white 939 0 0 940 0 0 yellow 841 -448 73 840 -448 72 cyan 678 150 -447 678 151 -448 green 578 -296 -376 578 -296 -375 magenta 426 296 376 426 296 375 red 325 -150 447 326 -151 448 blue 163 448 -73 164 448 -72 black 64 0 0 64 0 0 color y u v white 572 0 0 yellow 507 -250 57 cyan 401 84 -352 green 336 -165 -295 magenta 236 165 295 red 171 -84 352 blue 65 250 -57 black 0 0 0 color g r b white 1023 1023 1023 yellow 1023 1023 0 cyan 1023 0 1023 green 1023 0 1 magenta 0 1023 1022 red 0 1023 1 blue 0 0 1023 black 0 0 0 decoder output ccir 601 spec color y c b c r yc b c r
tmc22x5ya product specification 58 preliminary information simple luma color correction if the ybal register bit is set high, and the luma data reaches or exceeds the luma limits, there should be no c b c r or uv data at that time; therefore the color data are set to zero. if ybal is set low then the c b c r /uv data are unaffected by the luma data. c b c r msb inversion the msb of the c b c r data can be inverted by setting the msbo register bit high. as this would affect the chroma blanking level, this circuit appears at the output of the matrix circuit. output rounding for compatibility with 8 bit systems, the output of the matrix can be rounded to 8 bits by setting the rnd8 register bit high. output formats rgb outputs the rgb data are simply passed through to the decoder out- put. when the drsen register bit is high the drs data are inserted into the green data path only. yuv outputs the yuv data are simply passed through to the decoder out- put. when the drsen register bit is high the drs data are inserted into the luminance data path only. yc b c r outputs the yc b c r data can be output in 3 ways, depending upon the cdec, f422, and yuvt register bits. these output modes are summarized in . when cdec is high and f422 is high, the g/y output is set to 64 and the b/u output is set to 512 between the eav trs data word and the ?st preamble word of the sav trs, i.e. during the digital horizontal blanking period. when yuvt is high, r/v is set to 512, 64, 512, 64, etc., starting after the eav trs data word and ?ishing before the sav preamble. decimating c b c r data whenever the cdec register bit is set high the b/u and r/v data are simply sample dropped, with respect to cbsel, to produce the multiplexed c b c r data stream at the pck clock rate. if the input was initially d1 then the dropped samples will be the interpolated samples produced by the chroma interpolation ?ter. if however the c b c r data are simply weighted uv data then the sample dropped demodulated color difference signals (uv) will alias around 0.25 of the normalized sample frequency. multiplexed yc b c r output (trs words inserted) when both the cdec and yuvt register bits are high the y, c b , and c r component data are multiplexed into a single 27mhz (pxck) data stream with embedded trs words. the trs words are generated based on the hsync or vsync pulses provided to the decoder, and the internally derived horizontal blanking (hblk ), vertical blanking (vblk ), and the ?ld ?g (fld). this mode of operation is only available if a line locked pxck clock, at 27mhz, is provided. the trs words will be generated with respect to the hsync\ signal as per the ansi/smpte 125m-1992 and ccir 656 speci?ations. yc outputs the yc data are passed through to the decoder output. when the drsen register bit is high the drs data are inserted into the luminance data path only. the luminance appears on g/y, chrominance is on b/u and the r/v output is set to zero, by setting the v_scalar to zero. the ldv clock the decoder can accept clocks at either the pixel clock rate (pck) or at twice the pixel clock rate (pxck). in the cases where the clock provided is pxck, for example the genlock mode, the output data still needs to be at the pck clock rate. to aid in the design of external circuitry a ldv clock is pro- vided if the ldvio register bit is low, if ldvio is high then the ldv pin becomes an input for an external clock. if an external ldv clock is employed the user must ensure that the rising edge of the external ldv meets the speci?d setup and hold times relative to the input clock pin. the selection of which clock to use on the decoder output is set by the opsel register bit. when opsel is set low the output is clocked at the same rate as the clock on the clock pin, and when opsel is set high the output is clocked by the internal or external clock on the ldv pin. table 14. output format cdec yuvt f422 g/y b/u r/v comments 0 x x g or y b or c b r or c r [4:4:4] data 100y c b c r [4:2:2] data 101yc b c r 0 [4:2:2] data 11xyc b c r d1 data [4:2:2] data & d1 output
product specification tmc22x5ya 59 preliminary information sync pulse generator the vertical and horizontal references to the decoder can be from external vsync and hsync pulses, decoded from trs and trs-id words, or from the internal sync separator which extracts the sync information from the digitized input video. the sync pulse generator (spg) provides all the clock and enable pulses required to synchronize the decoder operation to the incoming video signal. these pulses are described below, along with the microprocessor data required to control them. internal field and line numbering scheme the internal line numbering of the digital decoder differs from the standard video line numbering as shown in the following tables. the internal line numbers for a 3 line comb advance the numbering by 1 line with respect to the input, but are identical with respect to the internally one line delayed decoded video. table 15. ntsc field and line numbering table 16. pal b,g,h,i field and line numbering table 17. pal m field and line numbering hstbg (burst gate) * the burst gate starts the 16 clock period average of the demodulated burst envelope. the position of the burst gate is programmed into a register as the number of clock periods from the falling edge of sync to the burst envelope. * signal is available over the microprocessor data bus. hblk (horizontal blanking period) * the horizontal blanking period is low between the start of sav and the end of eav. this signal is used in several places: a) to clear the sysph offset when low, this is required for correct operation of the subcarrier phase locked loop, b) to aid in the comb filter management, c) to remove the burst envelope on the demodulated uv data, d) to remove the syncs on the blue and red outputs. bblk (vertical burst blanking period) the vertical burst blanking blanks the lines with no burst from the burst phase locked loop. this signal is decoded from the line ident, lid 4-0 , and is modified by the video standard and the field count. mblk (mixed blanking) this signal is used in the matrix to switch between the sync scalar and the luma scalar. the mblk signal is active whenever hblk is active or becomes active when vblk becomes active. mblk is also active in pal on line 310 when both vact1 and fld are high and in ntsc and pal m on line 259 when vact2 is high and fld is low. fld * the fld is low for field 1 and high for field 2. lid 4-0 * the line id signals are used in the vertical comb filter management to control the comb filter on the leading and trailing lines of active video around the vertical blanking period, to start and stop the vindo operation, and in gener- ating the vertical blanking and burst blanking periods. vact2 * vact2 is high during the second half of all active lines. grabf * the grabf signal goes high when the internal field count is equal to the programmed field number for the grab operation. f a pixel grab is being, this signal is held high to not inhibit the grabs signal on each line. grabl * the grabl signal goes high when the internal line count is equal to the programmed line number for the grab operation. if a pixel grab is being performed, this signal is held high to not inhibit the grabs signal on each line. grabp * the grabp signal goes high when the internal pixel count is equal to the programmed pixel number for the grab operation. d vsync and dhsync (output pins) the dvsync and dhsync signals are active when gcr 2 is low. when gcr 2 is high these signals are three stated. three line comb based decoders have an inherent line delay, therefore the input vsync and hsync signals can not be just delayed by a few registers and output as d vsync and dhsync : they need to be delayed by one complete line. in all other comb ?ter con?urations the d vsync and standard field # standard line # internal field # internal line # 1 & 3 1 - 3 1 & 3 260 - 262 1 & 3 4 - 263 0 & 2 0 - 259 2 & 4 264 - 265 0 & 2 260 - 261 2 & 4 266 - 525 1 & 3 0 - 259 standard field # standard line # internal field # internal line # 1 & 5 1 - 312 0 & 4 0 - 311 2 & 6 313 - 625 1 & 5 0 - 312 3 & 7 626 - 937 2 & 6 0 - 311 4 & 8 938 - 1250 3 & 7 0 - 312 standard field # standard line # internal field # internal line # 1 & 5 1 - 262 0 & 2 0 - 261 2 & 6 263 - 525 1 & 3 0 - 262 3 & 7 1 - 262 0 & 2 0 - 261 4 & 8 263 - 525 1 & 3 0 - 262
tmc22x5ya product specification 60 preliminary information dhsync are referenced to the input data (0hflat) and not the output of the lstore1, i.e. 1hflat. the duration of the d vsync signal is ?ed to one line and the duration of the dhsync signal is 64 clock periods. both these signals are generated by the internal horizontal and vertical state machines. the falling edge of these signals relative to the data matches the requirements of the tmc22x91 family of digital encod- ers. avout active video (output pin) the decoder produces an active video signal starting 4 pck before the programmed start of active video and ending 4 pck after the programmed end of active video. this signal is used in both the video mixer (tmc22x8x) family and the digital encoder (tmc22x9x) family. the end points of this signal are ?gged by the internally generated sav and eav signals. vblk (vertical blanking period) ** the vertical blanking period conforms to the ccir 656 speci?ation for d1 component data streams. this signal is decoded from the line ident, lid 4-0 , and is active low. table 18. vertical blanking period bblk (vertical burst blanking period) the vertical burst blanking blanks the lines with no burst from the burst phase locked loop. this signal is controlled by the video standard and the ?ld count. the burst blanking signal is active low. ** signal is available over the microprocessor data bus. table 19. vertical burst blanking period lid 4-0 list of line idents the line numbers required to produce all the decoder control signals are summarized in internal ?ld no internal line no ntsc 0,2 0 - 5 260 & 261 1,3 0 - 6 260 - 262 pa l 0, 2, 4, & 6 0 - 21 310 & 311 1, 3, 5, & 7 0 - 22 311 & 312 pal-m 0, 2, 4, & 6 0 - 5 260 & 261 1, 3, 5, & 7 0 - 6 260 & 262 internal ?ld no internal line no ntsc 0,2 0 - 5 259 - 261 1,3 0 - 6 260 - 262 pa l 0 & 4 0 - 5 309 - 311 1 & 5 0 - 5 309 - 312 2 & 6 0 - 4 310 & 311 3 & 7 0 - 6 310 - 312 pal-m 0 & 4 0 - 7 259 - 261 1 & 5 0 - 7 259 - 262 2 & 6 0 - 6 258 & 261 3 & 7 0 - 6 260 - 262 table 20. table of line idents, lid[4:0] line no: lid 4-0 000 1 - 4 01 502 603 704 805 9 - 16 06 17 07 18 08 19 - 21 09 22 0a 23 0b 24 0c 25 - 257 0d 258 0e 259 0f
product specification tmc22x5ya 61 preliminary information timing parameters subcarrier programming the color subcarrier is produced by an internal 28 bit direct digital synthesizer (dds) which is phase locked to the burst signal of the digitized video input. the nominal frequency is programmed into the dds as follows: freq = (number of subcarrier cycles per line / number of pixels per line) * 2^28 an example would be ntsc subcarrier mode freq = (227.5 / 910) * 2^28 = 4000000 hex horizontal timing the horizontal video line is broken down into four horizontal timing parameters. sts: the number of pixels between sync pulses stb: the number of pixels between the nominal mid point of sync and the start of the 16 pixel burst gate. this value is modi?d depending upon the mode of operation. table 21. timing offsets btv: the number of pixels between the start of the 16 pixel burst gate and the nominal start of active video. av: the number of active pixels in the active video line. the difference between the sum of stb+btv+av sub- tracted from sts provides the nominal front porch. horizontal and vertical timing parameters when external horizontal and vertical syncs are provided the timing shown in figure 28 is required to synchronize the internal state machines to beginning of a ?ld (3, 5, or 7). for ?ld 2 (4, 6, or 8) the falling edge of vsync must occur at least 2 clock periods but not more than (h-2) clock periods after the falling edge of hsync , where h is the total num- ber of pixels in an active video line. 260 & 261 10 262 11 263 - 307 12 308 13 309 14 310 15 311 16 312 17 table 20. table of line idents, lid[4:0] (cont.) line no: lid 4-0 standard mode offset required x genlock -8 x line locked -8 x subcarrier -22 pal d2 mode -12 ntsc d2 mode -8 x d1 mode +12 figure 27. horizontal timing stb av 65-22x5y-68 sts btv
tmc22x5ya product specification 62 preliminary information figure 28. external hsync and vsync timing for field 1 (3, 5, or 7) vertical blanking figure 29. ntsc vertical interval clock t sp t hp 65-22x5y-12 hsync vsync 258 256 259 257 fields 2 and 4 fields 1 and 3 uvv uvv uve uvv ee ee ee ee es ee ss ss ss ss se ss ee ee ee ee eb eb ubb ubb ubb ubb uvv ubb uvv uvv uvv uvv 260 258 261 259 0 260 1 0 2 1 3 2 4 3 5 4 6 5 7 6 16 15 17 16 18 17 19 18 hsync vsync fld hsync vsync fld 65-22x5y-69
product specification tmc22x5ya 63 preliminary information figure 30. pal-b,g,h,i,n vertical interval 65-22x5y-70 fields 4 and 8 308 309 uvv uvv ee ee es ss ss ee ee eb -bb ubb ubb uvv uvv 31031101234 5 6 72122 ubb 23 24 309 310 fields 3 and 7 uvv -ve ee ee ss ss se ee ee ubb ubb uvv ubb uvv uvv 311 312 0 12 34 56 21 22 23 uvv 24 25 fields 2 and 6 308 309 uvv -vv ee ee es ss ss ee ee eb ubb ubb ubb uvv uvv 310 311 0 12 3456 7 21 22 ubb 23 24 309 310 fields 1 and 5 uvv -ve ee ee ss ss se ee ee -bb ubb uvv ubb uvv uvv 311 312 0 12 34 56 21 22 23 uvv 24 25 hsync vsync fld fld fld fld hsync vsync hsync vsync hsync vsync
tmc22x5ya product specification 64 preliminary information figure 31. pal-m vertical interval 65-22x5y-71 258 259 fields 2 and 6 uvv -ve ee ee es ss ss se ee ee eb -bb ubb ubb uvv uvv 2602610123456 7 816 17 18 258 257 259 fields 3 and 7 -vv uvv -ve ee ee es ss ss se ee ee eb ubb ubb ubb uvv uvv 26026101234567 816 17 18 258 259 fields 1 and 5 uvv uvv ee ee ee ss ss ss ee ee ee -bb ubb -bb ubb uvv 260261262012345 678 16 17 hsync hsync hsync hsync vsync vsync vsync vsync fld fld fld fld 258 259 fields 3 and 7 uvv -vv ee ee ee ss ss ss ee ee ee -bb ubb ubb ubb uvv 260261262012345 678 16 17
product specification tmc22x5ya 65 preliminary information vindo operation the vindo circuit uses the line idents on lid 4-0 , and the blanking signals to control the comb ?ter output and the blanking of the yuv data in the output matrix during the vertical blanking period. the vertical window vindo starts on the ?st line after the last equalizing pulse, at lid 4-0 = 02. the vindo stays high from this line until the vindo count = vindo 4-0 , or the vblk signal goes high, at which time the vindo goes low. while the vindo is high the decoder operation is controlled by vdiv, and during the time the vindo and vblk are low the decoder operation is controlled by vdov. table 22. pal vindo operation ntsc vindo operation video measurement the tmc22x5ya supports a comprehensive set of video measurement techniques to aid the user in setting up the gain, phase, etc. of the decoder and in tracking down system errors. pixel grab the pixel grab allows the user to grab one pixel every line, or one pixel out of the four ?ld sequence in ntsc or the 8 ?ld sequence in pal, under software control. the set pin can also be used to produce the pixel grab pulse if set 2-0 = 110 and pgext is set high. the 10 bit g/y, b/u, r/v outputs are stored in one set of four 8 bit registers in the format block, while the 10 bit luma and mixed sync data and the 10 bit demodulated u and v color difference signals are stored in a set of ?e 8 bit registers in the grab circuit block. the pixel grab signal, pixel, whether internally or externally generated, is inter- nally delayed to ensure that the all the grabbed data are from the same pixel relative to the line sync pulse. the pixel signal is equal to pgrab or the logical and of pgrab with fgrab and lgrab, and is controlled by the lpgen, pgen, and pgext register bits. the luma and mixed sync signals are multiplexed on the yms data bus and the u and v signals are multiplexed on the uv data bus, at the pxck clock rate. the pixel grab signal accommodates for this when grabbing these components. an example of the pixel grab feature, is grabbing a pixel in the center of the burst period allowing the user to check the burst height by reading the magnitude of the demodulated u and v components. this allows the user to compensate for any chrominance gain errors in the output matrix. lid 4-0 vindo vdiv vdov y c 00 - 01 x x x normal normal 02 - 0a 1 0 x simple simple 02 - 0a 1 1 x ?t black 02 - 0a 0 x 0 black black 02 - 0a 0 x 1 simple black 0b - 17 x x x normal normal lid 4-0 vindo vdiv vdov y c 00 - 02 x x x normal normal 03 - 06 1 0 x simple simple 03 - 06 1 1 x ?t black 03 - 06 0 x 0 black black 03 - 06 0 x 1 simple black 07 - 17 x x x normal normal figure 32. pixel grab locations video a video b pixel luma and chroma separation c data y data dt dt luma proc lpf y ms u v yms uv output matrix output formatter and buffer 65-22x5y-72 g/y b/u r/v lpf u data grab register 3a/3c register 3b/3c register 38/3c register 39/3c register 34/37 register 35/37 register 36/37 v data grab y data grab ms data grab g/y grab b/u grab rv grab chroma demodulation
tmc22x5ya product specification 66 preliminary information table 23. pixel grab control if a single pixel every 4 ?lds in ntsc and 8 ?lds in pal is required to be grabbed, pgg and pgen in register 30h should be set high. the pixel grab signal is the logical and of the grabp, grabl, and grabf signals. grabp goes high whenever the pixel count equals the programmed pixel grab number, grabl goes high for one line when- ever the line count equals the programmed line number, and the grabf goes high for a ?ld whenever the ?ld number equals the programmed ?ld count. if the same pixel on every line is required to be grabbed, then pgg should be set low, which internally forces grabl and grabf to be forced high enabling the pixel grab whenever grabp goes high. the set pin can be used to provide an external grab signal when pgext is set high in register 30h and the set function in register 00h, set[2:0] is programmed to 110 (binary). in this mode the falling edge on the set pin triggers the pixel grab. the grabp, grabl, and grabf signals are available on bits 0,1, and 2 respectively of the read only register 41. an example of the pixel grab feature, would be grabbing a pixel in the center of the burst period allowing the user to check the burst height by reading the magnitude of the demodu- lated u and v components. this would then allow the user to compensate for any chrominance gain errors in the output matrix. the pixel grab value is delayed by 29 pixels from the pixel count. this is the delay for all the pixel grab registers. figure 33 shows this delay relative to ghsync. this means that if 29 is placed in the pg value, the actual pixel grabbed is pixel 0. the top two bits of the pg value provide the quadrant and the bottom 9 bits provide the offset within that quadrant. the integer part of sts/4 gives the maximum count for each quadrant while the fractional result (bottom two bits) provides the 0,1,2, or 3 count offset for the last quadrant. for pixels value <= 4*int(sts/4) pg[10:9] = quadrant number pg[8:0] = max quadrant count - int(sts/4) + pixel offset for pixels value > 4*int(sts/4) the quadrant is always number 3, ie pg[10:9] = 11 while the pixel in excess of 4*int(sts/4) is added to 1536. lgext pgen pgext lgen grabs signal 0 0 x x grabs = 0 0 1 0 0 grabs = pgrab 0 1 0 1 grabs = fgrab & lgrab & pgrab 0 1 1 x grabs = not (set pin) 1 x 0 x grabs = pgrab 1 x 1 x grabs = not (set pin) figure 33. relationship between pixel count and pixel grab value sts-1 pixel sts-1 pixel 0 pixel grab value 28 29 pixels pixel grab value 0 pixel count pixel grab ghsync 0 1 0 sts-1 0
product specification tmc22x5ya 67 preliminary information examples: ntsc std with sts programmed to 858. base pixels per quadrant = int(858/4) = 214 pixel 0: 1. pixel 0 <= 4*int(858/4) 2. required pixel 0 < 214 therefore quadrant = 0, [pg[10:9] = 00] 3. pg[10:0] = 511 - 214 + (0+[0*214]) = 297 pixel 56: 1. pixel 56 <= 4*int(858/4) 2. required pixel 56 < 214 therefore quadrant = 0 [pg[10:9] = 00] 3. pg[10:0] = 511 - 214 + (56-[0*214]) = 353 pixel 250: 1. pixel 250 <= 4*int(858/4) 2. required pixel 250 > 214 therefore quadrant =/= 0 3. required pixel 250 < 428 therefore quadrant = 1, [pg[10:9] = 01] 4. pg[10:0] = 1023 - 214 + (250-[1*214]) = 845 pixel 800: 1. pixel 800 <= 4*int(858/4) 2. required pixel 800 > 214 therefore quadrant =/= 0 3. required pixel 800 > 428 therefore quadrant =/= 1 4. required pixel 800 > 642 therefore quadrant =/= 2 5. required pixel 800 < 858 therefore quadrant = 3, [pg[10:9] = 11] 6. pg[10:0]= 2047 - 214 + (800-[3*214]) = 1991 pixel 856: 1. pixel <= 4*int(858/4) 2. required pixel 856 > 214 therefore quadrant =/= 0 3. required pixel 856 > 428 therefore quadrant =/= 1 4. required pixel 856 > 642 therefore quadrant =/= 2 5. required pixel 856 < 858 therefore quadrant = 3, [pg[10:9] = 11] 6. pg[10:>0] = 2047 - 214 + (856-[3*214]) = 2047 pixel 857: 1. pixel 857 > 4*int(858/4) 2. therefore quadrant = 3, [pg[10:9] = 11] 3. pg[10:0] = 1536 + (857-[4*214]) = 1537 composite line grab the composite line grab is only available in the 3 line comb based decoders (tmc22053a and tmc22153a), and allows the user to grab any line from the 4 ?ld sequence in ntsc or 8 ?ld sequence in pal when lgen is set high. when the lgen register bit is set high the decoder auto- matically switches to operate as a ?imple?bandsplit decoder. the set pin can also be used to produce the line grab pulse if set 2-0 = 110 and lgext is set high. once the line grab has been activated the subcarrier oscilla- tor is frozen with the seed and phase from the beginning of the line, and the composite video in the 1h line store is frozen by disabling the write signals in lstore1. the read cycle for the frozen line store is still clocked by pck. the subcarrier dds and the internal read only registers will be updated once per clock period as normal, but will reload the drs seed and phase values at the beginning of each line. the g/y, b/u, and r/v outputs will remain active, and the dhsync and d vsync signals will remained locked to the input or ?wheel if the input has been removed. the pixel grab function can be used in conjunction with the frozen line to examine individual pixels inside the decoder. parallel microprocessor interface the parallel microprocessor interface, active when ser is high, employs a 12-line interface, with an 8-bit data bus and one address bit: two addresses are required for device programming and pointer-register management. address bit 0 selects between reading/writing the register addresses and reading/writing register data. when writing, the address is presented along with a low on the r/w pin during the fall- ing edge of cs eight bits of data are presented on d 7-0 dur- ing the subsequent rising edge of cs . one additional falling edge of cs is needed to move input data to its assigned working registers. in read mode, the address is accompanied by a high on the r/w pin during a falling edge of cs . the data output pins go to a low-impedance state t doz after cs falls. valid data are present on d 7-0 t dom after the falling edge of cs . because this port operates asynchronously with the pixel timing, there is an uncertainty in this data valid output delay of one pxck period. this uncertainty does not apply to t doz . writing data to speci? control registers of the tmc22x5ya requires that the 8-bit address of the control register of inter- est be written. this control register address is the base address for subsequent write operations. the base address autoincrements by one for each byte of data written after the data byte intended for the base address. if more bytes are transferred than there are available addresses, the address will not increment and remain at its maximum value of 3fh. table 24. parallel port control a 1-0 r/w action 00 0 load d 7-0 into control register pointer (block 00) 00 1 read control register pointer on d 7-0 01 0 load d 7-0 into addressed xlut location pointer (block 01) 01 1 read addressed xlut location pointer on d 7-0 . 10 0 write d 7-0 to addressed control register 10 1 read addressed control register on d 7-0 11 0 write d 7-0 to addressed xlut location 11 1 read addressed xlut location on d 7-0
tmc22x5ya product specification 68 preliminary information serial control port (r-bus) in addition to the 12-wire parallel port, a 2-wire serial control interface is provided, and active when ser is low. either port alone can control the entire chip. up to eight tmc22x5ya devices may be connected to the 2-wire serial interface with each device having a unique address. the 2-wire interface comprises a clock (scl) and a bi-direc- tional data (sda) pin. the decoder acts as a slave for receiv- ing and transmitting data over the serial interface. when the serial interface is not active, the logic levels on scl and sda are pulled high by external pull-up resistors. data received or transmitted on the sda line must be stable for the duration of the positive-going scl pulse. data on sda must change only when scl is low. if sda changes state while scl is high, the serial interface interprets that action as a start or stop sequence. there are six components to serial bus operation: start signal slave address byte block pointer base register address byte data byte to read or write stop signal when the serial interface is inactive (scl and sda are high) communications are initiated by sending a start sig- nal. the start signal is a high-to-low transition on sda while scl is high. this signal alerts all slaved devices that a data transfer sequence is coming. the ?st eight bits of data transferred after a start signal com- prise a seven bit slave address (the ?st seven bits) and a sin- gle r/w bit (the eighth bit). the r/w bit indicates the direction of data transfer, read from or write to the slave device. if the transmitted slave address matches the address of the device (set by the state of the sa 2-0 input pins in table 20), the tmc22x5ya acknowledges by bringing sda low on the 9th scl pulse. if the addresses do not match, the tmc22x5ya does not acknowledge. figure 33. microprocessor parallel port ?write timing figure 34. microprocessor parallel port ?read timing t pwlcs t sa t sd t ha t hd t pwhcs cs 65-22x5y-16 r/w adr d 7-0 t pwlcs t sa t dom t ha t hom t doz t pwhcs cs r/w adr d 7-0 65-22x5y-17
product specification tmc22x5ya 69 preliminary information table 25. serial port addresses data transfer via serial interface for each byte of data read or written, the msb is the ?st bit; that is, bit 7 of the 8-bit sequence. if the tmc22x5ya does not acknowledge the master device during a write sequence, the sda remains high so the mas- ter can generate a stop signal. if the master device does not acknowledge the tmc22x5ya during a read sequence, the decoder interprets this as ?nd of data.?the sda remains high so the master can generate a stop signal. writing data to speci? control registers of the tmc22x5ya requires that the 8-bit address of the control register of inter- est be written after the slave address has been established. this control register address is the base address for subse- quent write operations. the base address autoincrements by one for each byte of data written after the data byte intended for the base address. if more bytes are transferred than there are available addresses, the address will not increment and remain at its maximum value of 3fh. any base address higher than 3fh will not produce an acknowledge signal. data are read from the control registers of the tmc22x5ya in a similar manner. reading requires two data transfer operations: the base address must be written with the r/w\ bit of the slave address byte low to set up a sequential read operation. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 a 6 (msb) a 5 a 4 a 3 a 2 (sa 2 ) a 1 (sa 1 ) a 0 (sa 0 ) 1 01 1000 1 01 1001 1 01 1010 1 01 1011 1 01 1100 1 01 1101 1 01 1110 1 01 1111 reading (the r/w bit of the slave address byte high) begins at the previously established base address. the address of the read register autoincrements after each byte is transferred. to terminate a write sequence to the tmc22x5ya, a stop signal must be sent. a stop signal comprises a low-to- high transition of sda while scl is high. to terminate a read sequence simply do not acknowledge (noack) the last byte received and the tmc22x5ya will terminate the sequence. a repeated start signal occurs when the master device driv- ing the serial interface generates a start signal without ?st generating a stop signal to terminate the current communica- tion. this is used to change the mode of communication (read, write) between the slave and master without releasing the serial interface lines. serial interface read/write examples write to one control register start signal slave address byte (r/w bit = low) block pointer (00) base address byte data byte to base address stop signal write to four consecutive xlut locations start signal slave address byte (r/w bit = low) block pointer (01) base address byte data byte to base address data byte to (base address + 1) data byte to (base address + 2) data byte to (base address + 3) stop signal read from one xlut location start signal slave address byte (r/w bit = low) figure 35. serial port read/write timing t buff t stah t stasu t stosu t dho t dsu t dal t bah scl sda 65-22x5y-18
tmc22x5ya product specification 70 preliminary information block pointer (01) base address byte stop signal start signal slave address byte (r/w bit = high) data byte from base address stop signal read from four consecutive control registers start signal slave address byte (r/w bit = low) block pointer (00) base address byte stop signal start signal slave address byte (r/w bit = high) data byte from base address data byte from (base address + 1) data byte from (base address + 2) data byte from (base address + 3) stop signal figure 36. serial interface ?typical byte transfer sda 65-22x5y-19 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (msb) (lsb) ack scl figure 37. serial interface ?chip address sda 65-22x5y-19a a6 a5 a4 a3 a2 sa2 sa1 sa0 ack scl *note: to read from the xlut, the initial read must be a dummy read. this means, for example, to read back xlut location 0x02, read back location 0x01, then read back 0x02 and ignore the information read back from the 0x01 location. this only needs to be done once in a sequence. to read back the entire xlut, set the pointer to 0xff and ignore the data read from this register. the poin ter will then auto-increment to 0x00 allowing the next 256 locations read to be valid.
product specification tmc22x5ya 71 preliminary information equivalent circuits and threshold levels figure 38. equivalent digital input circuit figure 39. equivalent digital output figure 40. threshold levels for three-state digital input v dd p n 27014b gnd v dd p n 27011b gnd digital output t dis 0.5v 0.5v 2.0v 0.8v 65-22x5y-76 three-state outputs set or reset t ena
tmc22x5ya product specification 72 preliminary information absolute maximum ratings (beyond which the device may be damaged) 1 notes: 1. absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. functional operation under any of these conditions is not implied. performance and reliability are guaranteed only if operating conditions are not exceeded. 2. applied voltage must be current limited to specified range. 3. forcing voltage must be limited to specified range. 4. current is specified as conventional current flowing into the device. figure 41. input timing parameters parameter min. max. unit power supply voltage -0.5 +7.0 v digital inputs applied voltage -0.5 v dd +0.5 v forced current 3, 4 -20.0 +20.0 ma digital outputs applied voltage 2 -0.5 v dd +0.5 v forced current 3, 4 -3.0 +6.0 ma short circuit duration (single output in high state to ground) 1 second analog output short circuit duration (all outputs to ground) in?ite temperature operating, ambient -20 110 c junction 140 c lead, soldering (10 seconds) 300 c vapor phase soldering (1 minute) 220 c storage 150 c t sp2 t hp2 t clh t pwhck t pwlck 65-22x5y-77 pxck hsync cvbs internal pck ldv pixel 0 pixel 1 pixel 2 t spi t hpi
product specification tmc22x5ya 73 preliminary information operating conditions notes: 1. tested at f clk = 30mhz to aid in the understanding of the timing relationship between the pxck and ldv clock, when the ldv signal is used as the tmc22x5ya output clock, the following block diagram of the tmc22x5ya output stage is provided. figure 42. functional block diagram of the tmc22x5ya g/y, b/u, and r/v output stage parameter min. nom. max. units v dd power supply voltage 4.75 5.0 5.25 v v ih input voltage, logic high ttl compatible inputs 2.0 v dd v serial port (sda and scl) 0.7*v dd v v il input voltage, logic low ttl compatible inputs gnd 0.8 v serial port (sda and scl) gnd 0.3*v dd v i oh output current, logic high -2.0 ma i ol output current, logic low 4.0 ma t a ambient temperature, still air 0 70 c pixel interface (input) f clk pixel rate (cksel = 0) 10 18 mhz master clock rate = 2x pixel rate (cksel = 1) 1 20 36 mhz t pwhck clock pulse width, high 8 ns t pwlck clock pulse width, low 13 ns t sp pixel data input setup time 8 ns t hp pixel data input hold time 2 ns t sp hsync , vsync , and buffer setup time 5 ns t hp hsync , vsync , and buffer hold time 6 ns data in pxck g/y, b/u, and r/v output data ldv q d ck 2:1 mux q d ck 65-22x5y-78
tmc22x5ya product specification 74 preliminary information operating conditions (continued) figure 436974. output timing parameters parameter min. nom. max. units pixel interface (output) t pod clock to dhsync and dvysnc , avout, and fid [2:0] propagation time 41518ns t pod clock to data, propagation time 4 15 18 ns t pod int. or ext. ldv to data, propagation time 4 15 18 ns t hod clock to dhsync and dvsync , avout, and fid [2:0] hold time 2.5 ns t hod clock to data, hold time 2.5 ns t hod int. or ext. ldv to data, hold time 2.5 ns t ena enable to low z on output data 23 30 ns t dis disable to high z on output data 23 30 ns t clh clock to ldv (i/p) signal high 9 0 ns t clh clock to ldv (o/p) signal high 10 14 ns t pod t pod t clh 65-22x5y-79 pxck dhsync g/y, b/u rv data tmc22x5y internal pck ldv pixel 0 pixel 1 pixel 2
product specification tmc22x5ya 75 preliminary information operating conditions (continued) electrical characteristics notes: 1. typical i dd with v dd = nom and t a = nom, maximum i dd with v dd = 5.25v and t a = 70 c 2. g/y [9:0] , b/y [9:0] , r/v [9:0] , dvsync , dhsync , ldv, avout, fid [2:0] parameter min. nom. max. units parallel microprocessor interface t pwlcs cs pulse width, low 2 pixels t pwhcs cs pulse width, high 3 pixels t sa address setup time 8 ns t ha address hold time 2 ns t sd data setup time (write) 8 ns t hd data hold time (write) 2 ns serial microprocessor interface t dal scl pulse width , low 1.0 m s t dah scl pulse width, high 0.48 m s t stah hold time for start or repeated start 0.48 m s t stasu setup time for start or repeated start 0.48 m s t stosu setup time for stop 0.48 m s t buff bus free time betweeen a stop and a start condition 1.0 m s t dsu data setup time 80 ns parameter conditions min. typ. max. units i dd power supply current 1 v dd = max, f pxck = 27mhz 225 275 ma i ddq power supply current, disabled v dd = max 50 ma i ih input current, high v dd = max, v in = v dd 10 m a i il input current, low v dd = max, v in = 0v 10 m a i ozh hi-z output leakage current, output high v dd = max, v in = v dd 10 m a i ozl hi-z output leakage current, output low v dd = max, v in = 0v 10 m a i os short-circuit current -20 -80 ma v oh output voltage, high g/y 9-0 , etc 2 ., i oh = max 2.4 v v ol output voltage, low g/y 9-0 , etc 2 ., i ol = max 0.4 v sda, i ol = 3ma 0.4 v sda, i ol = 6ma 0.6 v c i digital input capacitance 4 10 pf c o digital output capacitance 10 pf
tmc22x5ya product specification 76 preliminary information switching characteristics note: timing reference points are at the 50% level, digital output load <40pf. system performance characteristics parameter conditions min. typ. max. units t doz output delay, cs to low-z 9 ns t hom output hold time, cs to high-z 10 ns t dom output delay, cs to data valid 30 40 ns parameter conditions min. typ. max. units res video processing resolution tmc2205xa 8 bits tmc2215xa 10 bits
tmc22x5ya product specification 77 preliminary information programming examples standard: ntsc-m mode: line-locked input format: 13.5 composite output format: rgb (0-1023) sync on green decoder: adaptive 3-line chroma comb filter register map: standard: ntsc mode: line-locked input format: ntsc composite output format: d1 component decoder: 3 line adaptive chroma comb register map: 0123456789 abcdef 0 d8 01 00 a1 20 28 00 10 40 00 12 00 00 04 24 09 1 5a 56 2e d2 23 00 00 2c 1b 90 13 49 f0 01 00 00 2 40 f8 e0 43 00 00 07 00 00 00 00 00 00 00 00 00 3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0123456789 abcdef 0 c0 01 00 a1 20 28 00 10 40 00 34 74 80 04 64 08 1 5a 56 2e d2 23 72 00 00 95 0e 51 49 40 00 00 00 2 40 f8 e0 43 24 25 07 00 00 00 00 00 00 00 00 00 3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
product specification tmc22x5ya 78 preliminary information programming examples (continued) standard: ntsc mode: line-locked input format: 13.5 mhz composite video output format: yuv decoder: adaptive 3-line comb register map: standard: pal mode: line-locked input format: composite output format: yuv decoder: adaptive 3-line comb register map: 0123456789 abcdef 0 d8 01 00 a1 20 28 00 10 40 00 34 00 80 04 64 08 1 5a 56 2e d2 23 3c 00 2c 1b 90 13 49 f0 01 00 00 2 40 f8 e0 43 24 25 07 00 00 00 00 00 00 00 00 00 3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0123456789 abcdef 0 db 01 00 24 08 00 24 15 40 08 36 00 c0 04 54 09 1 60 53 32 ce 23 01 00 00 00 3e 03 49 00 05 00 00 2 90 15 13 54 24 25 07 00 00 00 00 00 00 00 00 00 3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
tmc22x5ya product specification 79 preliminary information programming examples (continued) standard: pal mode: line-locked input format: pal-yc output format: y, cb, cr (d1 out) decoder: register map: no comb standard: ntsc-m mode: d1 mode input format: d1, c b yc r [y] multiplexed data w/embedded trs words output format: d1 output decoder: 2 line chroma comb of c b c r data register map: 0123456789 abcdef 0 d3 07 00 00 20 00 00 0c 40 08 24 60 03 00 0b 0a 1 60 53 44 d2 23 00 00 00 88 bf 3c 49 40 00 00 00 2 90 15 13 54 00 00 00 00 00 00 00 00 00 00 00 00 3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0123456789 abcdef 0 c0 1f 37 e3 20 00 00 0c 40 40 34 60 09 04 f8 02 1 5a 47 35 d2 23 00 0a 00 00 00 00 49 40 00 00 00 2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
product specification tmc22x5ya 80 preliminary information programming examples (continued) standard: ntsc-m mode: d1 mode input format: d1, c b yc r [y] multiplexed data w/trs output format: yc b c r , output dhsync + dvsync decoder: simple transcoder register map: standard: ntsc-m mode: d1 mode input format: yc b c r output format: d1, c b yc r [y] multiplexed data with trs decoder: simple transcoder register map: 0123456789 abcdef 0 c0 1f 37 e3 20 00 00 0c 40 40 34 00 09 04 0a 02 1 5a 47 35 d2 23 00 0a 00 00 00 00 49 40 00 00 00 2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0123456789 abcdef 0 c0 0f 07 a3 20 00 00 0c 40 00 34 60 09 04 0a 02 1 5a 47 35 d2 23 00 00 00 00 00 00 49 40 00 00 00 2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
tmc22x5ya product specification 81 preliminary information programming worksheet standard: mode: input format: output format: decoder: register map: the drs appears on the output at the rate. 0123456789 abcdef 0 1 2 xx xx xx xx xx xx xx xx xx -70 -60 -50 -40 -30 -20 -10 0 0.00 0.10 0.20 0.30 0.40 0.50 normalized frequency attenuation (db) 65-22x5y-40 bandsplit filter 1 bandsplit filter 2 bandsplit filter -70 -60 -50 -40 -30 -20 -10 0 0.00 0.10 0.20 0.30 0.40 0.50 normalized frequency attenuation (db) 65-22x5y-41 demodulator filter 1 demodulator filter 2 demodulation filter -70 -60 -50 -40 -30 -20 -10 0 0.00 0.10 0.20 0.30 0.40 0.50 normalized frequency attenuation (db) 65-22x5y-42 adaptive notch filter 1 adaptive notch filter 2 adaptive notch filter 3 adaptive notch filter -70 -60 -50 -40 -30 -20 -10 0 0.00 0.10 0.20 0.30 0.40 0.50 normalized frequency attenuation (db) 65-22x5y-43 non-adaptive notch filter
product specification tmc22x5ya 82 preliminary information notes
product specification tmc22x5ya 83 preliminary information mechanical dimensions ?100 lead mqfp package lead detail a1 aa2 b -c- lead coplanarity seating plane ccc c see lead detail e e1 d1 d b e base plane r c l a datum plane 0 ? min. .20 (.008) min. .13 (.30) .005 (.012) .13 (.005) r min. 0.063" ref (1.60mm) a .134 3.40 symbol inches min. max. min. max. millimeters notes a1 .010 .25 .015 .38 a2 .100 .120 2.55 3.05 b .009 3, 5 5 .23 .009 .23 c .005 .13 e .667 .687 16.95 17.45 .0256 bsc .65 bsc e l .025 .037 .65 .95 100 100 30 30 4 n nd 20 20 ne a 0 ? 7 ? 0 ? 7 ? .004 .10 ccc d .904 .923 22.95 23.45 d1 .783 .791 19.90 20.10 e1 .547 .555 13.90 14.10 notes: 1. 2. 3. 4. 5. all dimensions and tolerances conform to ansi y14.5m-1982. controlling dimension is millimeters. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "b" dimension. dambar cannot be located on the lower radius or the foot. "l" is the length of terminal for soldering to a substrate. "b" & "c" includes lead finish thickness.
tmc22x5ya product specification preliminary information 5/20/98 0.0m 001 stock#ds7022x5ya 1998 fairchild semiconductor corporation life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com ordering information product number temperature range decoding resolution package package marking tmc22051akhc 0 c to 70 c simple 8 bit 100-lead mqfp 22051akhc TMC22052Akhc 0 c to 70 c 2-line comb 8 bit 100-lead mqfp 22052akhc tmc22053akhc 0 c to 70 c 3-line comb 8 bit 100-lead mqfp 22053akhc tmc22151akhc 0 c to 70 c simple 10 bit 100-lead mqfp 22151akhc tmc22152akhc 0 c to 70 c 2-line comb 10 bit 100-lead mqfp 22152akhc tmc22153akhc 0 c to 70 c 3-line comb 10 bit 100-lead mqfp 22153akhc

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